mainboard/intel/glkrvp: Add support for GLKRVP

GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1

GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)

By default, CONFIG_GLK_CHROME_EC is selected for  external ChromeEC AIC
config.

Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/intel/glkrvp/boardid.c

@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <stddef.h>
+#include <ec/acpi/ec.h>
+
+#define BOARD_ID_GLK_RVP1_DDR4	0x5 /* RVP1 - DDR4 */
+#define BOARD_ID_GLK_RVP2_LP4SD	0x7 /* RVP2 - LP4 Solder Down */
+#define BOARD_ID_GLK_RVP2_LP4	0x8 /* RVP2 - LP4 Socket */
+#define EC_FAB_ID_CMD	0x0D /* Get the board fab ID in the lower 3 bits */
+
+uint8_t board_id(void)
+{
+	MAYBE_STATIC int id = -1;
+	if (id < 0) {
+		if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+			id = variant_board_id();
+		else {
+			if (send_ec_command(EC_FAB_ID_CMD) == 0)
+				id = (recv_ec_data() & 0x07);
+		}
+	}
+	return id;
+}