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mb/google/guybrush: Configure eSPI GPIOs in early stage

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BUG=b:181961514, b:180721208
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51295
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mathew King
2021-03-05 08:56:59 -07:00
committed by Felix Held
parent d490afbe04
commit d5baf6d89c
1 changed files with 11 additions and 11 deletions
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22
src/mainboard/google/guybrush/variants/baseboard/gpio.c
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@@ -108,16 +108,7 @@ static const struct soc_amd_gpio base_gpio_table[] = {
/* CLK_REQ0_L */ /* CLK_REQ0_L */
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
/* GPIO_93 - GPIO_103: Not available */ /* GPIO_93 - GPIO_103: Not available */
/* ESPI1_DATA0 */ /* GPIO_104 - GPIO_108: eSPI configured in early stage */
PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
/* ESPI1_DATA1 */
PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
/* ESPI1_DATA2 */
PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
/* ESPI1_DATA3 */
PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
/* ESPI_ALERT_L */
PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
/* RAM_ID_0 / DEV_BEEP_EN */ /* RAM_ID_0 / DEV_BEEP_EN */
PAD_GPI(GPIO_109, PULL_NONE), PAD_GPI(GPIO_109, PULL_NONE),
/* GPIO_110 - GPIO_112: Not available */ /* GPIO_110 - GPIO_112: Not available */
@@ -165,7 +156,16 @@ static const struct soc_amd_gpio base_gpio_table[] = {
/* Early GPIO configuration */ /* Early GPIO configuration */
static const struct soc_amd_gpio early_gpio_table[] = { static const struct soc_amd_gpio early_gpio_table[] = {
/* TODO: Fill early gpio configuration */ /* ESPI1_DATA0 */
PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
/* ESPI1_DATA1 */
PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
/* ESPI1_DATA2 */
PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
/* ESPI1_DATA3 */
PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
/* ESPI_ALERT_L */
PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
}; };
/* GPIO configuration for sleep */ /* GPIO configuration for sleep */