soc/intel/baytrail: Implement POSTCAR stage

Use common code to tear down CAR.

Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/baytrail/Makefile.inc

@@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/intel/turbo
 
 ramstage-y += memmap.c
 romstage-y += memmap.c
+postcar-y += memmap.c
 ramstage-y += tsc_freq.c
 romstage-y += tsc_freq.c
 smm-y += tsc_freq.c
@@ -20,6 +21,7 @@ ramstage-y += gfx.c
 ramstage-y += iosf.c
 romstage-y += iosf.c
 smm-y += iosf.c
+postcar-y += iosf.c
 ramstage-y += northcluster.c
 ramstage-y += ramstage.c
 ramstage-y += gpio.c
@@ -51,6 +53,8 @@ ramstage-y += hda.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S
+
 cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin
 
 CPPFLAGS_common += -Isrc/soc/intel/baytrail/include