soc/intel: Replace config_of_path() with config_of_soc()

The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.

Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.

Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/acpi.c

@@ -90,7 +90,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 void acpi_create_gnvs(struct global_nvs_t *gnvs)
 {
 	struct soc_intel_apollolake_config *cfg;
-	cfg = config_of_path(SA_DEVFN_ROOT);
+	cfg = config_of_soc();
 
 	/* Clear out GNVS. */
 	memset(gnvs, 0, sizeof(*gnvs));
@@ -152,7 +152,7 @@ int soc_madt_sci_irq_polarity(int sci)
 void soc_fill_fadt(acpi_fadt_t *fadt)
 {
 	const struct soc_intel_apollolake_config *cfg;
-	cfg = config_of_path(SA_DEVFN_ROOT);
+	cfg = config_of_soc();
 
 	fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
 

src/soc/intel/apollolake/chip.c

@@ -300,7 +300,7 @@ static void set_power_limits(void)
 	uint32_t tdp, min_power, max_power;
 	uint32_t pl2_val;
 
-	cfg = config_of_path(SA_DEVFN_ROOT);
+	cfg = config_of_soc();
 
 	if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
 		printk(BIOS_INFO, "Skip the RAPL settings.\n");
@@ -364,7 +364,7 @@ static void set_sci_irq(void)
 	struct soc_intel_apollolake_config *cfg;
 	uint32_t scis;
 
-	cfg = config_of_path(SA_DEVFN_ROOT);
+	cfg = config_of_soc();
 
 	/* Change only if a device tree entry exists. */
 	if (cfg->sci_irq) {

src/soc/intel/apollolake/cpu.c

@@ -296,7 +296,7 @@ void cpu_lock_sgx_memory(void)
 
 int soc_fill_sgx_param(struct sgx_param *sgx_param)
 {
-	config_t *conf = config_of_path(SA_DEVFN_ROOT);
+	config_t *conf = config_of_soc();
 
 	sgx_param->enable = conf->sgx_enable;
 	return 0;

src/soc/intel/apollolake/memmap.c

@@ -35,7 +35,7 @@ void *cbmem_top(void)
 	if (!CONFIG(SOC_INTEL_GLK))
 		return tolum;
 
-	config = config_of_path(PCH_DEVFN_LPC);
+	config = config_of_soc();
 
 	/* FSP allocates 2x PRMRR Size Memory for alignment */
 	if (config->sgx_enable)

src/soc/intel/apollolake/pmutil.c

@@ -148,7 +148,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 {
 	DEVTREE_CONST struct soc_intel_apollolake_config *config;
 
-	config = config_of_path(SA_DEVFN_ROOT);
+	config = config_of_soc();
 
 	/* Assign to out variable */
 	*dw0 = config->gpe0_dw1;

src/soc/intel/apollolake/pnpconfig.c

@@ -39,7 +39,7 @@ static void pnp_settings(void *unused)
 	const struct pnpconfig *pnpconfigarr;
 	struct soc_intel_apollolake_config *config;
 
-	config = config_of_path(SA_DEVFN_ROOT);
+	config = config_of_soc();
 
 	switch (config->pnp_settings) {
 	case PNP_PERF:

src/soc/intel/apollolake/romstage.c

@@ -95,7 +95,7 @@ static void soc_early_romstage_init(void)
 static void configure_thermal_target(void)
 {
 	msr_t msr;
-	const config_t *conf = config_of_path(SA_DEVFN_ROOT);
+	const config_t *conf = config_of_soc();
 
 	if (!conf->tcc_offset)
 		return;
@@ -269,7 +269,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
 	/* Only for GLK */
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 
-	const config_t *config = config_of_path(PCH_DEVFN_LPC);
+	const config_t *config = config_of_soc();
 
 	m_cfg->PrmrrSize = config->PrmrrSize;