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soc/intel: Replace config_of_path() with config_of_soc()

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The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.

Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.

Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2019-09-28 00:20:27 +03:00
committed by Patrick Georgi
parent d3d38c95b7
commit d5f645c6cd
46 changed files with 72 additions and 79 deletions
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8
src/soc/intel/skylake/acpi.c
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@@ -172,7 +172,7 @@ static int get_cores_per_package(void)
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = config_of_soc();
/* Set unknown wake source */
gnvs->pm1i = -1;
@@ -232,7 +232,7 @@ unsigned long acpi_fill_madt(unsigned long current)
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
config_t *config = config_of_path(SA_DEVFN_ROOT);
config_t *config = config_of_soc();
/* Use ACPI 3.0 revision */
fadt->header.revision = get_acpi_table_revision(FADT);
@@ -503,7 +503,7 @@ void generate_cpu_entries(struct device *device)
int totalcores = dev_count_cpu();
int cores_per_package = get_cores_per_package();
int numcpus = totalcores/cores_per_package;
config_t *config = config_of_path(SA_DEVFN_ROOT);
config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
@@ -674,7 +674,7 @@ void southbridge_inject_dsdt(struct device *device)
/* Save wake source information for calculating ACPI _SWS values */
int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
{
const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = config_of_soc();
struct chipset_power_state *ps;
static uint32_t gpe0_sts[GPE0_REG_MAX];
uint32_t pm1_en;