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sb/intel/i82801ix/i82801ix.c: Align with i82801jx

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Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
2020-08-10 13:32:18 +02:00
parent ab6ecb4d08
commit d5fde1c922
1 changed files with 2 additions and 5 deletions
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7
src/southbridge/intel/i82801ix/i82801ix.c
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@@ -35,7 +35,6 @@ static void i82801ix_pcie_init(const config_t *const info)
{ {
struct device *pciePort[6]; struct device *pciePort[6];
int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */
u32 reg32;
/* PCIe - BIOS must program... */ /* PCIe - BIOS must program... */
for (i = 0; i < 6; ++i) { for (i = 0; i < 6; ++i) {
@@ -44,8 +43,7 @@ static void i82801ix_pcie_init(const config_t *const info)
printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); printk(BIOS_EMERG, "PCIe port 00:1c.%x", i);
die(" is not listed in devicetree.\n"); die(" is not listed in devicetree.\n");
} }
reg32 = pci_read_config32(pciePort[i], 0x300); pci_or_config32(pciePort[i], 0x300, 1 << 21);
pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21));
pci_write_config8(pciePort[i], 0x324, 0x40); pci_write_config8(pciePort[i], 0x324, 0x40);
} }
@@ -85,10 +83,9 @@ static void i82801ix_pcie_init(const config_t *const info)
} }
/* Lock R/WO ASPM support bits. */ /* Lock R/WO ASPM support bits. */
for (i = 0; i < 6; ++i) { for (i = 0; i < 6; ++i)
pci_update_config32(pciePort[i], 0x4c, ~0, 0); pci_update_config32(pciePort[i], 0x4c, ~0, 0);
} }
}
static void i82801ix_ehci_init(void) static void i82801ix_ehci_init(void)
{ {