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soc/intel/apollolake: Use the new SPI driver interface

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1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash controller
in different files.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully for reef.

Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17562
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Furquan Shaikh
2016-11-21 12:41:20 -08:00
committed by Martin Roth
parent b5d41cb063
commit d6c555971b
8 changed files with 439 additions and 406 deletions
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4
src/soc/intel/apollolake/mmap_boot.c
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@ -22,9 +22,9 @@
#include <commonlib/region.h>
#include <console/console.h>
#include <fmap.h>
#include <soc/flash_ctrlr.h>
#include <soc/intel/common/nvm.h>
#include <soc/mmap_boot.h>
#include <soc/spi.h>
/*
* BIOS region on the flash is mapped right below 4GiB in the address
@ -81,7 +81,7 @@ static void bios_mmap_init(void)
* Base and Limit.
* Base and Limit fields are in units of 4KiB.
*/
uint32_t val = spi_ctrlr_reg_read(SPIBAR_BIOS_BFPREG);
uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG);
start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB;
bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>