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soc/intel/common/block: Move VTd basic definitions into header file

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TEST=Build and boot on intel/archercity CRB

Change-Id: I4f9e606cf9ec01ec157ef4dd7c26f6b5eb88c7b7
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jincheng Li
2024-06-02 20:53:25 +08:00
committed by Felix Held
parent 99a190105f
commit d6c58b79e7
2 changed files with 34 additions and 33 deletions
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34
src/soc/intel/common/block/include/intelblocks/vtd.h
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@@ -3,8 +3,42 @@
#ifndef SOC_INTEL_COMMON_BLOCK_VTD_H #ifndef SOC_INTEL_COMMON_BLOCK_VTD_H
#define SOC_INTEL_COMMON_BLOCK_VTD_H #define SOC_INTEL_COMMON_BLOCK_VTD_H
#include <device/mmio.h>
#include <stdint.h> #include <stdint.h>
/* VT-d specification: https://cdrdv2.intel.com/v1/dl/getContent/671081 */
#define VER_REG 0x0
#define CAP_REG 0x8
#define CAP_PMR_LO BIT(5)
#define CAP_PMR_HI BIT(6)
#define PMEN_REG 0x64
#define PMEN_EPM BIT(31)
#define PMEN_PRS BIT(0)
#define PLMBASE_REG 0x68
#define PLMLIMIT_REG 0x6C
#define PHMBASE_REG 0x70
#define PHMLIMIT_REG 0x78
static __always_inline uint32_t vtd_read32(uintptr_t vtd_base, uint32_t reg)
{
return read32p(vtd_base + reg);
}
static __always_inline void vtd_write32(uintptr_t vtd_base, uint32_t reg, uint32_t value)
{
return write32p(vtd_base + reg, value);
}
static __always_inline uint64_t vtd_read64(uintptr_t vtd_base, uint32_t reg)
{
return read64p(vtd_base + reg);
}
static __always_inline void vtd_write64(uintptr_t vtd_base, uint32_t reg, uint64_t value)
{
return write64p(vtd_base + reg, value);
}
/* /*
* Enable DMA protection by setting PMR registers in VT-d for whole DRAM memory. * Enable DMA protection by setting PMR registers in VT-d for whole DRAM memory.
*/ */

33
src/soc/intel/common/block/vtd/vtd.c
View File

@@ -12,19 +12,6 @@
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
/* VT-d specification: https://cdrdv2.intel.com/v1/dl/getContent/671081 */
#define VER_REG 0x0
#define CAP_REG 0x8
#define CAP_PMR_LO BIT(5)
#define CAP_PMR_HI BIT(6)
#define PMEN_REG 0x64
#define PMEN_EPM BIT(31)
#define PMEN_PRS BIT(0)
#define PLMBASE_REG 0x68
#define PLMLIMIT_REG 0x6C
#define PHMBASE_REG 0x70
#define PHMLIMIT_REG 0x78
/* FSP 2.x VT-d HOB from edk2-platforms */ /* FSP 2.x VT-d HOB from edk2-platforms */
static const uint8_t vtd_pmr_info_data_hob_guid[16] = { static const uint8_t vtd_pmr_info_data_hob_guid[16] = {
0x45, 0x16, 0xb6, 0x6f, 0x68, 0xf1, 0xbe, 0x46, 0x45, 0x16, 0xb6, 0x6f, 0x68, 0xf1, 0xbe, 0x46,
@@ -40,26 +27,6 @@ struct vtd_pmr_info_hob {
static struct vtd_pmr_info_hob *pmr_hob; static struct vtd_pmr_info_hob *pmr_hob;
static __always_inline uint32_t vtd_read32(uintptr_t vtd_base, uint32_t reg)
{
return read32p(vtd_base + reg);
}
static __always_inline void vtd_write32(uintptr_t vtd_base, uint32_t reg, uint32_t value)
{
return write32p(vtd_base + reg, value);
}
static __always_inline uint64_t vtd_read64(uintptr_t vtd_base, uint32_t reg)
{
return read64p(vtd_base + reg);
}
static __always_inline void vtd_write64(uintptr_t vtd_base, uint32_t reg, uint64_t value)
{
return write64p(vtd_base + reg, value);
}
static bool is_vtd_enabled(uintptr_t vtd_base) static bool is_vtd_enabled(uintptr_t vtd_base)
{ {
uint32_t version = vtd_read32(vtd_base, VER_REG); uint32_t version = vtd_read32(vtd_base, VER_REG);