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mainboards: Drop PWRS from GNVS

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Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.

Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2021-01-15 13:46:11 +02:00
parent e0936a56ec
commit d6ccbb9d48
44 changed files with 34 additions and 89 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/acpi/dsdt_top.asl
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@@ -7,3 +7,6 @@
#include <vendorcode/google/chromeos/acpi/gnvs.asl> #include <vendorcode/google/chromeos/acpi/gnvs.asl>
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif #endif
/* Power state (AC = 1) */
Name (PWRS, One)

1
src/mainboard/acer/g43t-am3/acpi_tables.c
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@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
} }

9
src/mainboard/asrock/g41c-gs/acpi_tables.c
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@@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_gnvs.h>
#include <soc/nvs.h>
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
}

1
src/mainboard/asus/p5qc/acpi_tables.c
View File

@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
} }

1
src/mainboard/asus/p5ql-em/acpi_tables.c
View File

@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
} }

9
src/mainboard/asus/p5qpl-am/acpi_tables.c
View File

@@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_gnvs.h>
#include <soc/nvs.h>
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
}

9
src/mainboard/foxconn/g41s-k/acpi_tables.c
View File

@@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_gnvs.h>
#include <soc/nvs.h>
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
}

1
src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
View File

@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
} }

4
src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl
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@@ -16,10 +16,6 @@
Name(OSV, Ones) /* Assume nothing */ Name(OSV, Ones) /* Assume nothing */
Name(PICM, One) /* Assume APIC */ Name(PICM, One) /* Assume APIC */
/* Variables used by EC */
/* TODO: These may belong in global non-volatile storage */
Name(PWRS, Zero)
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
Field(GP0B, ByteAcc, NoLock, Preserve) { Field(GP0B, ByteAcc, NoLock, Preserve) {

9
src/mainboard/intel/dg41wv/acpi_tables.c
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@@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_gnvs.h>
#include <soc/nvs.h>
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
}

1
src/mainboard/intel/dg43gt/acpi_tables.c
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@@ -5,6 +5,5 @@
void mainboard_fill_gnvs(struct global_nvs *gnvs) void mainboard_fill_gnvs(struct global_nvs *gnvs)
{ {
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
} }

4
src/mainboard/lenovo/g505s/acpi/mainboard.asl
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@@ -16,10 +16,6 @@
Name(OSV, Ones) /* Assume nothing */ Name(OSV, Ones) /* Assume nothing */
Name(PICM, One) /* Assume APIC */ Name(PICM, One) /* Assume APIC */
/* Variables used by EC */
/* TODO: These may belong in global non-volatile storage */
Name(PWRS, Zero)
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
Field(GP0B, ByteAcc, NoLock, Preserve) { Field(GP0B, ByteAcc, NoLock, Preserve) {

9
src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c
View File

@@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_gnvs.h>
#include <soc/nvs.h>
void mainboard_fill_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
}

2
src/soc/amd/picasso/acpi/globalnvs.asl
View File

@@ -14,7 +14,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Miscellaneous */ /* Miscellaneous */
, 8, // 0x00 - Processor Count , 8, // 0x00 - Processor Count
LIDS, 8, // 0x01 - LID State LIDS, 8, // 0x01 - LID State
PWRS, 8, // 0x02 - AC Power State , 8, // 0x02 - AC Power State
CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console
PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index
GPEI, 64, // 0x0f - 0x16 - GPE Wake Source GPEI, 64, // 0x0f - 0x16 - GPE Wake Source

2
src/soc/amd/picasso/include/soc/nvs.h
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@@ -16,7 +16,7 @@ struct __packed global_nvs {
/* Miscellaneous */ /* Miscellaneous */
uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t unused_was_pcnt; /* 0x00 - Processor Count */
uint8_t lids; /* 0x01 - LID State */ uint8_t lids; /* 0x01 - LID State */
uint8_t pwrs; /* 0x02 - AC Power State */ uint8_t unused_was_pwrs; /* 0x02 - AC Power State */
uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */
uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */

2
src/soc/amd/stoneyridge/acpi/globalnvs.asl
View File

@@ -11,7 +11,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Miscellaneous */ /* Miscellaneous */
, 8, // 0x00 - Processor Count , 8, // 0x00 - Processor Count
LIDS, 8, // 0x01 - LID State LIDS, 8, // 0x01 - LID State
PWRS, 8, // 0x02 - AC Power State , 8, // 0x02 - AC Power State
CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console
PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index
GPEI, 64, // 0x0f - 0x16 - GPE Wake Source GPEI, 64, // 0x0f - 0x16 - GPE Wake Source

2
src/soc/amd/stoneyridge/include/soc/nvs.h
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@@ -16,7 +16,7 @@ struct __packed global_nvs {
/* Miscellaneous */ /* Miscellaneous */
uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t unused_was_pcnt; /* 0x00 - Processor Count */
uint8_t lids; /* 0x01 - LID State */ uint8_t lids; /* 0x01 - LID State */
uint8_t pwrs; /* 0x02 - AC Power State */ uint8_t unused_was_pwrs; /* 0x02 - AC Power State */
uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */
uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */

2
src/soc/intel/apollolake/acpi/globalnvs.asl
View File

@@ -12,7 +12,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
, 8, // 0x00 - Processor Count , 8, // 0x00 - Processor Count
PPCM, 8, // 0x01 - Max PPC State PPCM, 8, // 0x01 - Max PPC State
LIDS, 8, // 0x02 - LID State LIDS, 8, // 0x02 - LID State
PWRS, 8, // 0x03 - AC Power State , 8, // 0x03 - AC Power State
DPTE, 8, // 0x04 - Enable DPTF DPTE, 8, // 0x04 - Enable DPTF
CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console
PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index

2
src/soc/intel/apollolake/include/soc/nvs.h
View File

@@ -16,7 +16,7 @@ struct __packed global_nvs {
uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t unused_was_pcnt; /* 0x00 - Processor Count */
uint8_t ppcm; /* 0x01 - Max PPC State */ uint8_t ppcm; /* 0x01 - Max PPC State */
uint8_t lids; /* 0x02 - LID State */ uint8_t lids; /* 0x02 - LID State */
uint8_t pwrs; /* 0x03 - AC Power State */ uint8_t unused_was_pwrs; /* 0x03 - AC Power State */
uint8_t dpte; /* 0x04 - Enable DPTF */ uint8_t dpte; /* 0x04 - Enable DPTF */
uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */

2
src/soc/intel/baytrail/acpi/globalnvs.asl
View File

@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, /* 0x0a - Lock function parameter */ PRM5, 8, /* 0x0a - Lock function parameter */
P80D, 32, /* 0x0b - Debug port (IO 0x80) value */ P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
LIDS, 8, /* 0x0f - LID state (open = 1) */ LIDS, 8, /* 0x0f - LID state (open = 1) */
PWRS, 8, /* 0x10 - Power State (AC = 1) */ , 8, /* 0x10 - Power State (AC = 1) */
, 8, /* 0x11 - Processor count */ , 8, /* 0x11 - Processor count */
TPMP, 8, /* 0x12 - TPM Present and Enabled */ TPMP, 8, /* 0x12 - TPM Present and Enabled */
TLVL, 8, /* 0x13 - Throttle Level */ TLVL, 8, /* 0x13 - Throttle Level */

2
src/soc/intel/baytrail/include/soc/nvs.h
View File

@@ -19,7 +19,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 unused_was_pcnt; /* 0x11 - Processor Count */ u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */ u8 tlvl; /* 0x13 - Throttle Level */

2
src/soc/intel/braswell/acpi/globalnvs.asl
View File

@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, /* 0x0a - Lock function parameter */ PRM5, 8, /* 0x0a - Lock function parameter */
P80D, 32, /* 0x0b - Debug port (IO 0x80) value */ P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
LIDS, 8, /* 0x0f - LID state (open = 1) */ LIDS, 8, /* 0x0f - LID state (open = 1) */
PWRS, 8, /* 0x10 - Power State (AC = 1) */ , 8, /* 0x10 - Power State (AC = 1) */
, 8, /* 0x11 - Processor count */ , 8, /* 0x11 - Processor count */
TPMP, 8, /* 0x12 - TPM Present and Enabled */ TPMP, 8, /* 0x12 - TPM Present and Enabled */
TLVL, 8, /* 0x13 - Throttle Level */ TLVL, 8, /* 0x13 - Throttle Level */

2
src/soc/intel/braswell/include/soc/nvs.h
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@@ -19,7 +19,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 unused_was_pcnt; /* 0x11 - Processor Count */ u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */ u8 tlvl; /* 0x13 - Throttle Level */

2
src/soc/intel/broadwell/include/soc/nvs.h
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@@ -29,7 +29,7 @@ struct __packed global_nvs {
u8 s3u0; /* 0x14 - Enable USB in S3 */ u8 s3u0; /* 0x14 - Enable USB in S3 */
u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 s33g; /* 0x15 - Enable 3G in S3 */
u8 lids; /* 0x16 - LID State */ u8 lids; /* 0x16 - LID State */
u8 pwrs; /* 0x17 - AC Power State */ u8 unused_was_pwrs; /* 0x17 - AC Power State */
u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */

2
src/soc/intel/broadwell/pch/acpi/globalnvs.asl
View File

@@ -29,7 +29,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
S3U0, 8, // 0x14 - Enable USB in S3 S3U0, 8, // 0x14 - Enable USB in S3
S33G, 8, // 0x15 - Enable 3G in S3 S33G, 8, // 0x15 - Enable 3G in S3
LIDS, 8, // 0x16 - LID State LIDS, 8, // 0x16 - LID State
PWRS, 8, // 0x17 - AC Power State , 8, // 0x17 - AC Power State
, 32, // 0x18 - 0x1b - CBMEM TOC , 32, // 0x18 - 0x1b - CBMEM TOC
CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit

2
src/soc/intel/common/block/acpi/acpi/globalnvs.asl
View File

@@ -13,7 +13,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PPCM, 8, // 0x04 - Max PPC State PPCM, 8, // 0x04 - Max PPC State
TLVL, 8, // 0x05 - Throttle Level Limit TLVL, 8, // 0x05 - Throttle Level Limit
LIDS, 8, // 0x06 - LID State LIDS, 8, // 0x06 - LID State
PWRS, 8, // 0x07 - AC Power State , 8, // 0x07 - AC Power State
CBMC, 32, // 0x08 - 0x0b AC Power State CBMC, 32, // 0x08 - 0x0b AC Power State
PM1I, 64, // 0x0c - 0x13 PM1 wake status bit PM1I, 64, // 0x0c - 0x13 PM1 wake status bit
GPEI, 64, // 0x14 - 0x17 GPE wake status bit GPEI, 64, // 0x14 - 0x17 GPE wake status bit

2
src/soc/intel/common/block/include/intelblocks/nvs.h
View File

@@ -13,7 +13,7 @@ struct __packed global_nvs {
u8 ppcm; /* 0x04 - Max PPC State */ u8 ppcm; /* 0x04 - Max PPC State */
u8 tlvl; /* 0x05 - Throttle Level Limit */ u8 tlvl; /* 0x05 - Throttle Level Limit */
u8 lids; /* 0x06 - LID State */ u8 lids; /* 0x06 - LID State */
u8 pwrs; /* 0x07 - AC Power State */ u8 unused_was_pwrs; /* 0x07 - AC Power State */
u32 cbmc; /* 0x08 - 0xb coreboot Memory Console */ u32 cbmc; /* 0x08 - 0xb coreboot Memory Console */
u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */
u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ u64 gpei; /* 0x14 - 0x1b GPE wake status bit */

2
src/soc/intel/denverton_ns/acpi/globalnvs.asl
View File

@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, // 0x0a - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1) LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1) , 8, // 0x10 - Power State (AC = 1)
, 8, // 0x11 - Processor count , 8, // 0x11 - Processor count
TPMP, 8, // 0x12 - TPM Present and Enabled TPMP, 8, // 0x12 - TPM Present and Enabled
TLVL, 8, // 0x13 - Throttle Level TLVL, 8, // 0x13 - Throttle Level

2
src/soc/intel/denverton_ns/include/soc/nvs.h
View File

@@ -17,7 +17,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 unused_was_pcnt; /* 0x11 - Processor Count */ u8 unused_was_pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */ u8 tlvl; /* 0x13 - Throttle Level */

2
src/soc/intel/quark/include/soc/nvs.h
View File

@@ -7,7 +7,7 @@
struct __packed global_nvs { struct __packed global_nvs {
uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
uint8_t pwrs; /* 0x4 - Power state (AC = 1) */ uint8_t unused_was_pwrs; /* 0x4 - Power state (AC = 1) */
/* Required for future unified acpi_save_wake_source. */ /* Required for future unified acpi_save_wake_source. */
uint32_t pm1i; uint32_t pm1i;

2
src/soc/intel/skylake/acpi/globalnvs.asl
View File

@@ -29,7 +29,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
S3U0, 8, // 0x14 - Enable USB in S3 S3U0, 8, // 0x14 - Enable USB in S3
S33G, 8, // 0x15 - Enable 3G in S3 S33G, 8, // 0x15 - Enable 3G in S3
LIDS, 8, // 0x16 - LID State LIDS, 8, // 0x16 - LID State
PWRS, 8, // 0x17 - AC Power State , 8, // 0x17 - AC Power State
, 32, // 0x18 - 0x1b - CBMEM TOC , 32, // 0x18 - 0x1b - CBMEM TOC
CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit

2
src/soc/intel/skylake/include/soc/nvs.h
View File

@@ -29,7 +29,7 @@ struct __packed global_nvs {
u8 s3u0; /* 0x14 - Enable USB in S3 */ u8 s3u0; /* 0x14 - Enable USB in S3 */
u8 s33g; /* 0x15 - Enable 3G in S3 */ u8 s33g; /* 0x15 - Enable 3G in S3 */
u8 lids; /* 0x16 - LID State */ u8 lids; /* 0x16 - LID State */
u8 pwrs; /* 0x17 - AC Power State */ u8 unused_was_pwrs; /* 0x17 - AC Power State */
u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */ u32 obsolete_cmem; /* 0x18 - 0x1b - CBMEM TOC */
u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */ u32 cbmc; /* 0x1c - 0x1f - coreboot Memory Console */
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */

2
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
View File

@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, // 0x0a - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1) LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1) , 8, // 0x10 - Power State (AC = 1)
/* Thermal policy */ /* Thermal policy */
Offset (0x11), Offset (0x11),
TLVL, 8, // 0x11 - Throttle Level Limit TLVL, 8, // 0x11 - Throttle Level Limit

2
src/southbridge/intel/bd82x6x/include/soc/nvs.h
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@@ -19,7 +19,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
/* Thermal policy */ /* Thermal policy */
u8 tlvl; /* 0x11 - Throttle Level Limit */ u8 tlvl; /* 0x11 - Throttle Level Limit */
u8 flvl; /* 0x12 - Current FAN Level */ u8 flvl; /* 0x12 - Current FAN Level */

2
src/southbridge/intel/i82801gx/acpi/globalnvs.asl
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@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, // 0x0a - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1) LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1) , 8, // 0x10 - Power State (AC = 1)
DBGS, 8, // 0x11 - Debug State DBGS, 8, // 0x11 - Debug State
LINX, 8, // 0x12 - Linux OS LINX, 8, // 0x12 - Linux OS
DCKN, 8, // 0x13 - PCIe docking state DCKN, 8, // 0x13 - PCIe docking state

2
src/southbridge/intel/i82801gx/include/soc/nvs.h
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@@ -19,7 +19,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 dbgs; /* 0x11 - Debug state */ u8 dbgs; /* 0x11 - Debug state */
u8 linx; /* 0x12 - Linux OS */ u8 linx; /* 0x12 - Linux OS */
u8 dckn; /* 0x13 - PCIe docking state */ u8 dckn; /* 0x13 - PCIe docking state */

2
src/southbridge/intel/i82801ix/acpi/globalnvs.asl
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@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, // 0x0a - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1) LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1) , 8, // 0x10 - Power State (AC = 1)
DBGS, 8, // 0x11 - Debug State DBGS, 8, // 0x11 - Debug State
LINX, 8, // 0x12 - Linux OS LINX, 8, // 0x12 - Linux OS
DCKN, 8, // 0x13 - PCIe docking state DCKN, 8, // 0x13 - PCIe docking state

2
src/southbridge/intel/i82801ix/include/soc/nvs.h
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@@ -19,7 +19,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 dbgs; /* 0x11 - Debug state */ u8 dbgs; /* 0x11 - Debug state */
u8 linx; /* 0x12 - Linux OS */ u8 linx; /* 0x12 - Linux OS */
u8 dckn; /* 0x13 - PCIe docking state */ u8 dckn; /* 0x13 - PCIe docking state */

2
src/southbridge/intel/i82801jx/acpi/globalnvs.asl
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@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, // 0x0a - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1) LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1) , 8, // 0x10 - Power State (AC = 1)
DBGS, 8, // 0x11 - Debug State DBGS, 8, // 0x11 - Debug State
LINX, 8, // 0x12 - Linux OS LINX, 8, // 0x12 - Linux OS
DCKN, 8, // 0x13 - PCIe docking state DCKN, 8, // 0x13 - PCIe docking state

2
src/southbridge/intel/i82801jx/include/soc/nvs.h
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@@ -18,7 +18,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
u8 dbgs; /* 0x11 - Debug state */ u8 dbgs; /* 0x11 - Debug state */
u8 linx; /* 0x12 - Linux OS */ u8 linx; /* 0x12 - Linux OS */
u8 dckn; /* 0x13 - PCIe docking state */ u8 dckn; /* 0x13 - PCIe docking state */

2
src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
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@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, // 0x0a - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1) LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1) , 8, // 0x10 - Power State (AC = 1)
/* Thermal policy */ /* Thermal policy */
Offset (0x11), Offset (0x11),
TLVL, 8, // 0x11 - Throttle Level Limit TLVL, 8, // 0x11 - Throttle Level Limit

2
src/southbridge/intel/ibexpeak/include/soc/nvs.h
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@@ -20,7 +20,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
/* Thermal policy */ /* Thermal policy */
u8 tlvl; /* 0x11 - Throttle Level Limit */ u8 tlvl; /* 0x11 - Throttle Level Limit */
u8 flvl; /* 0x12 - Current FAN Level */ u8 flvl; /* 0x12 - Current FAN Level */

2
src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
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@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PRM5, 8, // 0x0a - Lock function parameter PRM5, 8, // 0x0a - Lock function parameter
P80D, 32, // 0x0b - Debug port (IO 0x80) value P80D, 32, // 0x0b - Debug port (IO 0x80) value
LIDS, 8, // 0x0f - LID state (open = 1) LIDS, 8, // 0x0f - LID state (open = 1)
PWRS, 8, // 0x10 - Power State (AC = 1) , 8, // 0x10 - Power State (AC = 1)
/* Thermal policy */ /* Thermal policy */
Offset (0x11), Offset (0x11),
TLVL, 8, // 0x11 - Throttle Level Limit TLVL, 8, // 0x11 - Throttle Level Limit

2
src/southbridge/intel/lynxpoint/include/soc/nvs.h
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@@ -19,7 +19,7 @@ struct __packed global_nvs {
u8 prm5; /* 0x0a - Lock function parameter */ u8 prm5; /* 0x0a - Lock function parameter */
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */ u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
/* Thermal policy */ /* Thermal policy */
u8 tlvl; /* 0x11 - Throttle Level Limit */ u8 tlvl; /* 0x11 - Throttle Level Limit */
u8 flvl; /* 0x12 - Current FAN Level */ u8 flvl; /* 0x12 - Current FAN Level */