src/cpu: Capitalize CPU, APIC and IOAPIC typo fix

Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16276
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker

src/cpu/intel/car/cache_as_ram_ht.inc

@@ -87,7 +87,7 @@ addrsize_no_MSR:
 	movl	$0x0f, %edx
 
 	/* Preload high word of address mask (in %edx) for Variable
-	 * MTRRs 0 and 1 and enable local apic at default base.
+	 * MTRRs 0 and 1 and enable local APIC at default base.
 	 */
 addrsize_set_high:
 	xorl	%eax, %eax

src/cpu/intel/ep80579/ep80579_init.c

@@ -34,7 +34,7 @@ static void ep80579_init(struct device *dev)
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 };
 

src/cpu/intel/fsp_model_206ax/model_206ax_init.c

@@ -386,7 +386,7 @@ static void model_206ax_init(struct device *cpu)
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	enable_lapic_tpr();
 	setup_lapic();
 

src/cpu/intel/fsp_model_406dx/model_406dx_init.c

@@ -182,7 +182,7 @@ static void model_406dx_init(struct device *cpu)
 
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Enable virtualization */

src/cpu/intel/haswell/haswell_init.c

@@ -720,7 +720,7 @@ static void haswell_init(struct device *cpu)
 	/* Clear out pending MCEs */
 	configure_mca();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	enable_lapic_tpr();
 	setup_lapic();
 

src/cpu/intel/model_1067x/model_1067x_init.c

@@ -32,7 +32,7 @@
 
 static void init_timer(void)
 {
-	/* Set the apic timer to no interrupts and periodic mode */
+	/* Set the APIC timer to no interrupts and periodic mode */
 	lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
 
 	/* Set the divider to 1, no divider */
@@ -322,7 +322,7 @@ static void model_1067x_init(struct device *cpu)
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Initialize the APIC timer */

src/cpu/intel/model_106cx/model_106cx_init.c

@@ -124,7 +124,7 @@ static void model_106cx_init(struct device *cpu)
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Enable virtualization */

src/cpu/intel/model_2065x/model_2065x_init.c

@@ -379,7 +379,7 @@ static void model_2065x_init(struct device *cpu)
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	enable_lapic_tpr();
 	setup_lapic();
 

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -572,7 +572,7 @@ static void model_206ax_init(struct device *cpu)
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	enable_lapic_tpr();
 	setup_lapic();
 

src/cpu/intel/model_65x/model_65x_init.c

@@ -36,7 +36,7 @@ static void model_65x_init(struct device *dev)
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 };
 

src/cpu/intel/model_67x/model_67x_init.c

@@ -40,7 +40,7 @@ static void model_67x_init(struct device *cpu)
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 }
 

src/cpu/intel/model_68x/model_68x_init.c

@@ -44,7 +44,7 @@ static void model_68x_init(struct device *cpu)
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 }
 

src/cpu/intel/model_69x/model_69x_init.c

@@ -18,7 +18,7 @@ static void model_69x_init(struct device *dev)
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 };
 

src/cpu/intel/model_6bx/model_6bx_init.c

@@ -44,7 +44,7 @@ static void model_6bx_init(struct device *cpu)
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 }
 

src/cpu/intel/model_6dx/model_6dx_init.c

@@ -31,7 +31,7 @@ static void model_6dx_init(struct device *dev)
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 };
 

src/cpu/intel/model_6ex/model_6ex_init.c

@@ -154,7 +154,7 @@ static void model_6ex_init(struct device *cpu)
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Enable virtualization */

src/cpu/intel/model_6fx/model_6fx_init.c

@@ -177,7 +177,7 @@ static void model_6fx_init(struct device *cpu)
 	/* Setup Page Attribute Tables (PAT) */
 	// TODO set up PAT
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Enable virtualization */

src/cpu/intel/model_6xx/model_6xx_init.c

@@ -31,7 +31,7 @@ static void model_6xx_init(struct device *dev)
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 };
 

src/cpu/intel/model_f0x/model_f0x_init.c

@@ -31,7 +31,7 @@ static void model_f0x_init(struct device *dev)
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 };
 

src/cpu/intel/model_f1x/model_f1x_init.c

@@ -31,7 +31,7 @@ static void model_f1x_init(struct device *dev)
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 };
 

src/cpu/intel/model_f2x/model_f2x_init.c

@@ -36,7 +36,7 @@ static void model_f2x_init(struct device *cpu)
 		intel_update_microcode_from_cbfs();
 	}
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Start up my CPU siblings */

src/cpu/intel/model_f3x/model_f3x_init.c

@@ -36,7 +36,7 @@ static void model_f3x_init(struct device *cpu)
 		intel_update_microcode_from_cbfs();
 	}
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Start up my CPU siblings */

src/cpu/intel/model_f4x/model_f4x_init.c

@@ -36,7 +36,7 @@ static void model_f4x_init(struct device *cpu)
 		intel_update_microcode_from_cbfs();
 	}
 
-	/* Enable the local CPU apics */
+	/* Enable the local CPU APICs */
 	setup_lapic();
 
 	/* Start up my CPU siblings */

src/cpu/intel/speedstep/speedstep.c

@@ -110,7 +110,7 @@ static void speedstep_get_limits(sst_params_t *const params)
  * @brief Generate full p-states table from processor parameters
  *
  * This is generic code and should work at least for Merom and Penryn
- * processors. It is used to generate acpi tables and configure EMTTM.
+ * processors. It is used to generate ACPI tables and configure EMTTM.
  */
 void speedstep_gen_pstates(sst_table_t *const table)
 {