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build system: Structure and serialize INTERMEDIATE

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Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.

Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).

While at it, also add the addition to the PHONY target so we don't
forget it.

BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.

Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Georgi
2021-01-12 15:09:57 +01:00
parent 725596622d
commit d6eb72c87e
12 changed files with 22 additions and 56 deletions
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8
src/cpu/intel/fit/Makefile.inc
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@@ -6,18 +6,14 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)
PHONY+=add_mcu_fit
INTERMEDIATE+=add_mcu_fit
add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL)
$(call add_intermediate, add_mcu_fit, $(obj)/coreboot.pre $(IFITTOOL))
@printf " UPDATE-FIT Microcode\n"
$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT
# Second FIT in TOP_SWAP bootblock
ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
PHONY+=add_ts_mcu_fit
INTERMEDIATE+=add_ts_mcu_fit
add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL)
$(call add_intermediate, add_ts_mcu_fit, $(obj)/coreboot.pre $(IFITTOOL))
@printf " UPDATE-FIT Top Swap: Microcode\n"
ifneq ($(FIT_ENTRY),)
$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT