mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips
Add the stub MPIO chips that contain the PCIe engine configuration for the external PCIe interfaces to the devicetree. Birman's port_descriptors_phoenix.c was used as a reference. The static configuration in the devicetree assumes that the default WLAN0_WWAN0 is selected; for the other cases we'll still need to fix up things accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still need to be handled in a follow-up patch. Since openSIL currently doesn't use the info from the gpio_group struct element, but deasserts both PCIe reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip configuration in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held
@@ -43,25 +43,75 @@ chip soc/amd/phoenix
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device domain 0 on
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device domain 0 on
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device ref iommu on end
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device ref iommu on end
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chip vendorcode/amd/opensil/chip/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "0"
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register "end_lane" = "7"
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register "aspm" = "ASPM_L1"
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register "clk_req" = "CLK_REQ0"
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# register "gpio_group" is currently not used
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device ref gpp_bridge_1_1 on end # MXM
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device ref gpp_bridge_1_1 on end # MXM
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device ref gpp_bridge_1_2 on
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end
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chip vendorcode/amd/opensil/chip/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "8"
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register "end_lane" = "11"
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register "aspm" = "ASPM_L1"
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register "clk_req" = "CLK_REQ1"
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device ref gpp_bridge_1_2 on # NVMe SSD1
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# Required so the NVMe gets placed into D3 when entering S0i3.
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# Required so the NVMe gets placed into D3 when entering S0i3.
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chip drivers/pcie/rtd3/device
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chip drivers/pcie/rtd3/device
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register "name" = ""NVME""
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register "name" = ""NVME""
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device pci 00.0 on end
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device pci 00.0 on end
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end
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end
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end # NVMe SSD1
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end
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end
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chip vendorcode/amd/opensil/chip/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "12"
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register "end_lane" = "12"
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register "aspm" = "ASPM_DISABLED"
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register "clk_req" = "CLK_REQ6"
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device ref gpp_bridge_1_3 on end # GBE
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device ref gpp_bridge_1_3 on end # GBE
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end
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chip vendorcode/amd/opensil/chip/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "13"
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register "end_lane" = "13"
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register "aspm" = "ASPM_DISABLED"
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register "clk_req" = "CLK_REQ5"
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device ref gpp_bridge_2_1 on end # SD
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device ref gpp_bridge_2_1 on end # SD
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end
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chip vendorcode/amd/opensil/chip/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "14"
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register "end_lane" = "14"
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register "aspm" = "ASPM_DISABLED"
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register "clk_req" = "CLK_REQ4"
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device ref gpp_bridge_2_2 on end # WWAN
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device ref gpp_bridge_2_2 on end # WWAN
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end
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chip vendorcode/amd/opensil/chip/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "15"
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register "end_lane" = "15"
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register "aspm" = "ASPM_DISABLED"
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register "clk_req" = "CLK_REQ3"
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device ref gpp_bridge_2_3 on end # WIFI
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device ref gpp_bridge_2_3 on end # WIFI
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device ref gpp_bridge_2_4 on
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end
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chip vendorcode/amd/opensil/chip/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "16"
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register "end_lane" = "19"
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register "aspm" = "ASPM_DISABLED"
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register "clk_req" = "CLK_REQ2"
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device ref gpp_bridge_2_4 on # NVMe SSD0
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# Required so the NVMe gets placed into D3 when entering S0i3.
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# Required so the NVMe gets placed into D3 when entering S0i3.
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chip drivers/pcie/rtd3/device
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chip drivers/pcie/rtd3/device
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register "name" = ""NVME""
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register "name" = ""NVME""
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device pci 00.0 on end
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device pci 00.0 on end
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end
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end
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end # NVMe SSD0
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end
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end
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device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
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device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
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device ref gfx on end # Internal GPU (GFX)
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device ref gfx on end # Internal GPU (GFX)
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device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
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device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
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@@ -109,7 +109,8 @@ if SOC_AMD_PHOENIX_BASE
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config CHIPSET_DEVICETREE
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config CHIPSET_DEVICETREE
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string
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string
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default "soc/amd/phoenix/chipset.cb"
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default "soc/amd/phoenix/chipset_fsp.cb" if SOC_AMD_PHOENIX_FSP
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default "soc/amd/phoenix/chipset_opensil.cb"
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config EARLY_RESERVED_DRAM_BASE
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config EARLY_RESERVED_DRAM_BASE
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hex
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hex
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170
src/soc/amd/phoenix/chipset_opensil.cb
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170
src/soc/amd/phoenix/chipset_opensil.cb
Normal file
@@ -0,0 +1,170 @@
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# TODO: Update for Phoenix
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chip soc/amd/phoenix
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device cpu_cluster 0 on
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ops amd_cpu_bus_ops
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end
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device domain 0 on
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ops phoenix_pci_domain_ops
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device pci 00.0 alias gnb on ops phoenix_root_complex_operations end
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device pci 00.2 alias iommu off ops amd_iommu_ops end
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device pci 01.0 on end # Dummy device function, do not disable
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# The PCIe GPP aliases in this SoC match the device and function numbers
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chip vendorcode/amd/opensil/chip/mpio
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device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end
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end
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chip vendorcode/amd/opensil/chip/mpio
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device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end
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end
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chip vendorcode/amd/opensil/chip/mpio
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device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end
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end
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chip vendorcode/amd/opensil/chip/mpio
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device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end
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end
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device pci 02.0 on end # Dummy device function, do not disable
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# The PCIe GPP aliases in this SoC match the device and function numbers
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chip vendorcode/amd/opensil/chip/mpio
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device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end
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end
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chip vendorcode/amd/opensil/chip/mpio
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device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end
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end
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chip vendorcode/amd/opensil/chip/mpio
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device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end
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end
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chip vendorcode/amd/opensil/chip/mpio
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device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end
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end
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chip vendorcode/amd/opensil/chip/mpio
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device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end
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end
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chip vendorcode/amd/opensil/chip/mpio
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device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end
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end
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device pci 03.0 on end # Dummy device function, do not disable
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device pci 03.1 alias usb4_pcie_bridge_0 off end
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device pci 04.0 on end # Dummy device function, do not disable
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device pci 04.1 alias usb4_pcie_bridge_1 off end
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device pci 08.0 on end # Dummy device function, do not disable
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device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
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ops amd_internal_pcie_gpp_ops
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device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX)
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device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
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device pci 0.2 alias crypto off end # Crypto Coprocessor
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device pci 0.3 alias xhci_0 off
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ops xhci_pci_ops
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chip drivers/usb/acpi
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register "type" = "UPC_TYPE_HUB"
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device usb 0.0 alias xhci_0_root_hub off
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chip drivers/usb/acpi
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device usb 3.0 alias usb3_port2 off end
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end
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chip drivers/usb/acpi
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device usb 3.1 alias usb3_port3 off end
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end
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chip drivers/usb/acpi
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device usb 2.0 alias usb2_port2 off end
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end
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chip drivers/usb/acpi
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device usb 2.1 alias usb2_port3 off end
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end
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chip drivers/usb/acpi
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device usb 2.2 alias usb2_port4 off end
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end
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chip drivers/usb/acpi
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device usb 2.3 alias usb2_port5 off end
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end
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chip drivers/usb/acpi
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device usb 2.4 alias usb2_port6 off end
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end
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end
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end
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end
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device pci 0.4 alias xhci_1 off
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ops xhci_pci_ops
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chip drivers/usb/acpi
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register "type" = "UPC_TYPE_HUB"
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device usb 0.0 alias xhci_1_root_hub off
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chip drivers/usb/acpi
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device usb 3.0 alias usb3_port7 off end
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end
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chip drivers/usb/acpi
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device usb 2.0 alias usb2_port7 off end
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end
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end
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end
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end
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device pci 0.5 alias acp off ops amd_acp_ops end # Audio Processor (ACP)
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device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
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device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
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end
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device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
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ops amd_internal_pcie_gpp_ops
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device pci 0.0 on end # dummy, do not disable
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device pci 0.1 alias ipu off end
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end
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device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
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ops amd_internal_pcie_gpp_ops
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device pci 0.0 on end # dummy, do not disable
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device pci 0.3 alias usb4_xhci_0 off
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ops xhci_pci_ops
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chip drivers/usb/acpi
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register "type" = "UPC_TYPE_HUB"
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device usb 0.0 alias usb4_xhci_0_root_hub off
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chip drivers/usb/acpi
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device usb 3.0 alias usb3_port0 off end
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end
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chip drivers/usb/acpi
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device usb 2.0 alias usb2_port0 off end
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end
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end
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end
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end
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device pci 0.4 alias usb4_xhci_1 off
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ops xhci_pci_ops
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chip drivers/usb/acpi
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register "type" = "UPC_TYPE_HUB"
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device usb 0.0 alias usb4_xhci_1_root_hub off
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chip drivers/usb/acpi
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device usb 3.0 alias usb3_port1 off end
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end
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chip drivers/usb/acpi
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device usb 2.0 alias usb2_port1 off end
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end
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end
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end
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end
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device pci 0.5 alias usb4_router_0 off end
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device pci 0.6 alias usb4_router_1 off end
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end
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device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function
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device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end
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device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end
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device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end
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device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end
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device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end
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device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end
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device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end
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device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end
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device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end
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end
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device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
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device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end
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device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end
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device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
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device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
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device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
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end
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Reference in New Issue
Block a user