diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 358ba75e04..56feab994e 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -17,8 +17,8 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
-#include <cbmem.h>
 #include <arch/acpi.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 2182ce7a46..5b75db0342 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -19,18 +19,12 @@
 
 #include <commonlib/cbmem_id.h>
 #include <rules.h>
-/* Delegation of resume backup memory so we don't have to
- * (slowly) handle backing up OS memory in romstage.c
- */
-#define CBMEM_BOOT_MODE		0x610
-#define CBMEM_RESUME_BACKUP	0x614
-#define CBMEM_FSP_HOB_PTR	0x614
-
-#ifndef __ASSEMBLER__
 #include <stddef.h>
 #include <stdint.h>
 #include <boot/coreboot_tables.h>
 
+#define CBMEM_FSP_HOB_PTR	0x614
+
 struct cbmem_entry;
 
 /*
@@ -151,7 +145,4 @@ void set_top_of_ram(uint64_t ramtop);
 void backup_top_of_ram(uint64_t ramtop);
 #endif
 
-#endif /* __ASSEMBLER__ */
-
-
 #endif /* _CBMEM_H_ */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index af5bd485e8..7b0efd1176 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -196,6 +196,12 @@
 
 #define DMIDRCCFG	0xeb4	/* 32bit */
 
+/* Delegation of resume backup memory so we don't have to
+ * (slowly) handle backing up OS memory in romstage.c
+ */
+#define CBMEM_BOOT_MODE		0x610
+#define CBMEM_RESUME_BACKUP	0x614
+
 #ifndef __ASSEMBLER__
 static inline void barrier(void) { asm("" ::: "memory"); }