Define some variables that were not defined. There are a couple left.

Do kbuildall then grep not.defined kbuildall.results/*
The interesting ones were GENERATE_*  I had to put them in twice to make it work
correctly: once outside the menu setting the defaults, and once inside the menu.
Now they show up when they should, and are always defined

Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0
in newconfig.
Define MEM_TRAIN_SEQ to be an integer and set it correctly.
Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10
MOVNTI is a performance enhancement, and should default to 0 so it doesn't break
boards that forget to define it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
2009-10-26 15:14:07 +00:00
parent 074356ec81
commit d73c1b5bf1
45 changed files with 187 additions and 145 deletions

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@@ -24,7 +24,7 @@
/* leave some space for global variable to pass to RAM stage */
#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
/* for CONFIG_CAR_FAM10 */
/* for CAR with FAM10 */
#define CacheSizeAPStack 0x400 /* 1K */
#define MSR_FAM10 0xC001102A

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@@ -103,9 +103,6 @@ static void post_cache_as_ram(void)
// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
#ifndef CONFIG_MEM_TRAIN_SEQ
#define CONFIG_MEM_TRAIN_SEQ 0
#endif
set_sysinfo_in_ram(1); // So other core0 could start to train mem
#if CONFIG_MEM_TRAIN_SEQ == 1

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@@ -1,6 +1,5 @@
config CPU_AMD_MODEL_10XXX
bool
select HAVE_INIT_TIMER
select HAVE_MOVNTI
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM

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@@ -306,11 +306,6 @@ static void STOP_CAR_AND_CPU()
stop_this_cpu();
}
#ifndef CONFIG_MEM_TRAIN_SEQ
#define CONFIG_MEM_TRAIN_SEQ 0
#endif
#if RAMINIT_SYSINFO == 1
static u32 init_cpus(u32 cpu_init_detectedx ,struct sys_info *sysinfo)
#else
@@ -478,8 +473,8 @@ static void start_node(u8 node)
/* Enable routing table */
printk_debug("Start node %02x", node);
#if CONFIG_CAR_FAM10 == 1
/* For CONFIG_CAR_FAM10 support, we need to set Dram base/limit for the new node */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
/* For FAM10 support, we need to set Dram base/limit for the new node */
pci_write_config32(NODE_MP(node), 0x44, 0);
pci_write_config32(NODE_MP(node), 0x40, 3);
#endif

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@@ -1,6 +1,5 @@
config CPU_AMD_MODEL_FXX
bool
select HAVE_INIT_TIMER
select HAVE_MOVNTI
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM

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@@ -215,11 +215,6 @@ static void STOP_CAR_AND_CPU(void)
stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp ....
}
#ifndef CONFIG_MEM_TRAIN_SEQ
#define CONFIG_MEM_TRAIN_SEQ 0
#endif
#if CONFIG_MEM_TRAIN_SEQ == 1
static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall);
#endif

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@@ -27,7 +27,6 @@ uses CONFIG_CPU_SOCKET_TYPE
uses CONFIG_CBB
uses CONFIG_CDB
uses CONFIG_PCI_BUS_SEGN_BITS
uses CONFIG_CAR_FAM10
config chip.h
@@ -39,8 +38,6 @@ default CONFIG_EXT_CONF_SUPPORT=0
default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG
default CONFIG_CPU_SOCKET_TYPE=0x11
default CONFIG_CAR_FAM10=1
if CONFIG_EXT_RT_TBL_SUPPORT
default CONFIG_CBB=0xff
default CONFIG_CDB=0

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@@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_AM2R2
bool
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select CAR_FAM10
config CPU_SOCKET_TYPE
hex

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@@ -27,7 +27,6 @@ uses CONFIG_CPU_SOCKET_TYPE
uses CONFIG_CBB
uses CONFIG_CDB
uses CONFIG_PCI_BUS_SEGN_BITS
uses CONFIG_CAR_FAM10
config chip.h
@@ -39,8 +38,6 @@ default CONFIG_EXT_CONF_SUPPORT=0
default CONFIG_DIMM_SUPPORT=0x0104 #DDR2 and REG
default CONFIG_CPU_SOCKET_TYPE=0x10
default CONFIG_CAR_FAM10=1
if CONFIG_EXT_RT_TBL_SUPPORT
default CONFIG_CBB=0xff
default CONFIG_CDB=0

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@@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_F_1207
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
select CAR_FAM10
config CPU_SOCKET_TYPE
hex