soc/intel/quark: Set the UPD values for MemoryInit
Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
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@ -19,11 +19,21 @@
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#define _SOC_CHIP_H_
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#include <stdint.h>
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#include <fsp/util.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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struct soc_intel_quark_config {
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uint32_t junk;
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/*
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* MemoryInit:
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*
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* The following fields come from FspUpdVpd.h and are defined as PCDs
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* for the FSP binary. Data for these fields comes from the board's
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* devicetree.cb file which gets processed into static.c and then
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* built into the coreboot image. The fields below contain retain
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* the FSP PCD field name.
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*/
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UINT16 PcdSmmTsegSize;
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};
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extern struct chip_operations soc_ops;
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