mb/system76/rpl: Add Galago Pro 7 as a variant
Change-Id: Iafbf858a8b90bb491b906ac817a6e1accf59363c Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
committed by
Tim Crawford
Tim Crawford
parent
35bed98ceb
commit
d773694493
@ -22,7 +22,6 @@ config BOARD_SYSTEM76_RPL_COMMON
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select SYSTEM_TYPE_LAPTOP
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config BOARD_SYSTEM76_ADDW3
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def_bool n
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select BOARD_SYSTEM76_RPL_COMMON
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select DRIVERS_GFX_NVIDIA
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select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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@ -34,7 +33,6 @@ config BOARD_SYSTEM76_ADDW3
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select SOC_INTEL_ALDERLAKE_PCH_S
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config BOARD_SYSTEM76_BONW15
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def_bool n
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select BOARD_SYSTEM76_RPL_COMMON
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select DRIVERS_GFX_NVIDIA
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select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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@ -44,8 +42,12 @@ config BOARD_SYSTEM76_BONW15
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select PCIEXP_HOTPLUG
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select SOC_INTEL_ALDERLAKE_PCH_S
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config BOARD_SYSTEM76_GALP7
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select BOARD_SYSTEM76_RPL_COMMON
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select PCIEXP_HOTPLUG
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select SOC_INTEL_ALDERLAKE_PCH_P
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config BOARD_SYSTEM76_GAZE18
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def_bool n
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select BOARD_SYSTEM76_RPL_COMMON
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select DRIVERS_GFX_NVIDIA
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select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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@ -55,7 +57,6 @@ config BOARD_SYSTEM76_GAZE18
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select TPM_RDRESP_NEED_DELAY
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config BOARD_SYSTEM76_ORYP11
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def_bool n
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select BOARD_SYSTEM76_RPL_COMMON
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select DRIVERS_GFX_NVIDIA
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select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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@ -65,7 +66,6 @@ config BOARD_SYSTEM76_ORYP11
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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config BOARD_SYSTEM76_SERW13
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def_bool n
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select BOARD_SYSTEM76_RPL_COMMON
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select DRIVERS_GFX_NVIDIA
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select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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@ -83,6 +83,7 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "serw13" if BOARD_SYSTEM76_SERW13
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@ -93,6 +94,7 @@ config OVERRIDE_DEVICETREE
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config MAINBOARD_PART_NUMBER
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "serw13" if BOARD_SYSTEM76_SERW13
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@ -100,6 +102,7 @@ config MAINBOARD_PART_NUMBER
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Adder WS" if BOARD_SYSTEM76_ADDW3
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default "Bonobo WS" if BOARD_SYSTEM76_BONW15
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default "Galago Pro" if BOARD_SYSTEM76_GALP7
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default "Gazelle" if BOARD_SYSTEM76_GAZE18
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default "Oryx Pro" if BOARD_SYSTEM76_ORYP11
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default "Serval WS" if BOARD_SYSTEM76_SERW13
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@ -107,6 +110,7 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
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config MAINBOARD_VERSION
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "serw13" if BOARD_SYSTEM76_SERW13
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@ -144,7 +148,7 @@ config TPM_MEASURED_BOOT
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default y
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config UART_FOR_CONSOLE
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default 0 if BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11
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default 0 if BOARD_SYSTEM76_GALP7 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11
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default 2 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_SERW13
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# PM Timer Disabled, saves power
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@ -4,6 +4,9 @@ config BOARD_SYSTEM76_ADDW3
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config BOARD_SYSTEM76_BONW15
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bool "bonw15"
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config BOARD_SYSTEM76_GALP7
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bool "galp7"
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config BOARD_SYSTEM76_GAZE18
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bool "gaze18"
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12
src/mainboard/system76/rpl/variants/galp7/board.fmd
Normal file
12
src/mainboard/system76/rpl/variants/galp7/board.fmd
Normal file
@ -0,0 +1,12 @@
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FLASH 32M {
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SI_DESC 4K
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SI_ME 4824K
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SI_BIOS@16M 16M {
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RW_MRC_CACHE 64K
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SMMSTORE(PRESERVE) 256K
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WP_RO {
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FMAP 4K
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COREBOOT(CBFS)
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}
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}
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}
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2
src/mainboard/system76/rpl/variants/galp7/board_info.txt
Normal file
2
src/mainboard/system76/rpl/variants/galp7/board_info.txt
Normal file
@ -0,0 +1,2 @@
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Board name: galp7
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Release year: 2023
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BIN
src/mainboard/system76/rpl/variants/galp7/data.vbt
Normal file
BIN
src/mainboard/system76/rpl/variants/galp7/data.vbt
Normal file
Binary file not shown.
227
src/mainboard/system76/rpl/variants/galp7/gpio.c
Normal file
227
src/mainboard/system76/rpl/variants/galp7/gpio.c
Normal file
@ -0,0 +1,227 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
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PAD_NC(GPD2, NONE),
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
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PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
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PAD_NC(GPD7, NONE),
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
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PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN#
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PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
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PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
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PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
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PAD_NC(GPP_A6, NONE),
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PAD_NC(GPP_A7, NONE),
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PAD_NC(GPP_A8, NONE),
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
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PAD_NC(GPP_A11, NONE),
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PAD_CFG_GPI(GPP_A12, NONE, DEEP), // SATAGP1
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PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
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// GPP_A14 (DGPU_PWR_EN) configured in bootblock
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PAD_CFG_GPI(GPP_A15, NONE, DEEP), // USB_OC2#
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
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PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
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PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
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PAD_NC(GPP_A20, NONE),
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PAD_NC(GPP_A21, NONE),
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PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN
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PAD_NC(GPP_A23, NONE),
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/* ------- GPIO Group GPP_B ------- */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
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// GPP_B2 (DGPU_RST#_PCH) configured in bootblock
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PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
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PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), // GPP_B5_I2C2_SDA (Pantone)
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), // GPP_B6_I2C2_SCL (Pantone)
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PAD_NC(GPP_B7, NONE),
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PAD_NC(GPP_B8, NONE),
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// GPP_B9 missing
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// GPP_B10 missing
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PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
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PAD_NC(GPP_B14, NONE), // TOP SWAP OVERRIDE strap
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PAD_NC(GPP_B15, NONE),
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_NC(GPP_B18, NONE), // NO REBOOT strap
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// GPP_B19 missing
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// GPP_B20 missing
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// GPP_B21 missing
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// GPP_B22 missing
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PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
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PAD_NC(GPP_C2, NONE), // TLS CONFIDENTIALITY strap
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
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PAD_CFG_GPO(GPP_C5, 1, PLTRST), // GPIO_LANRTD3
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
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// GPP_C8 missing
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// GPP_C9 missing
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// GPP_C10 missing
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// GPP_C11 missing
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// GPP_C12 missing
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// GPP_C13 missing
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// GPP_C14 missing
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// GPP_C15 missing
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// GPP_C16 missing
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// GPP_C17 missing
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// GPP_C18 missing
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// GPP_C19 missing
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// GPP_C20 missing
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// GPP_C21 missing
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// GPP_C22 missing
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// GPP_C23 missing
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/* ------- GPIO Group GPP_D ------- */
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PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
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PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
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PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
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PAD_NC(GPP_D3, NONE),
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PAD_NC(GPP_D4, NONE),
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// GPP_D5 (SSD1_CLKREQ#) configured by FSP
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PAD_NC(GPP_D6, NONE),
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// GPP_D7 (WLAN_CLKREQ#) configured by FSP
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// GPP_D8 (PEG_CLKREQ#) configured by FSP
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PAD_NC(GPP_D9, NONE),
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PAD_NC(GPP_D10, NONE), // TBT LSX #2 PINS VCCIO CONFIGURATION strap
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PAD_NC(GPP_D11, NONE),
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PAD_NC(GPP_D12, NONE), // TBT LSX #3 PINS VCCIO CONFIGURATION strap
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PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
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PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD1_PWR_EN#
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
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_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
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PAD_NC(GPP_E2, NONE),
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PAD_CFG_GPO(GPP_E3, 1, DEEP), // PCH_WLAN_EN
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PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR
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PAD_NC(GPP_E5, NONE), // DEVSLP1
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PAD_NC(GPP_E6, NONE), // JTAG ODT DISABLE strap
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PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
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PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
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PAD_NC(GPP_E10, NONE), // strap
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PAD_NC(GPP_E11, NONE), // strap
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PAD_NC(GPP_E12, NONE),
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PAD_NC(GPP_E13, NONE), // BOARD_ID4
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
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PAD_NC(GPP_E15, NONE),
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PAD_NC(GPP_E16, NONE),
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PAD_NC(GPP_E17, NONE), // BOARD_ID5
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// GPP_E18 (TBT_LSX0_TXD) configured by FSP
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// GPP_E19 (TBT_LSX0_RXD) configured by FSP
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PAD_NC(GPP_E20, NONE),
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PAD_NC(GPP_E21, NONE), // TBT LSX #1 PINS VCCIO CONFIGURATION strap
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PAD_NC(GPP_E22, NONE),
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PAD_NC(GPP_E23, NONE),
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
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PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
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PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
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PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
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// GPP_F5 (CNVI_CLKREQ) configured by FSP
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
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PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
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// GPP_F8 missing
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PAD_NC(GPP_F9, NONE),
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PAD_CFG_GPO(GPP_F10, 1, DEEP), // GPIO_CARD_PLT_RST#
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PAD_NC(GPP_F11, NONE), // BOARD_ID3
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PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
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PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
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PAD_NC(GPP_F14, NONE), // BOARD_ID1
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PAD_NC(GPP_F15, NONE), // BOARD_ID2
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PAD_CFG_GPO(GPP_F16, 1, DEEP), // GPU_EVENT#
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PAD_NC(GPP_F17, NONE), // GPIO_CARD_PWR
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PAD_CFG_GPO(GPP_F18, 0, DEEP), // dGPU_OVRM
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// GPP_F19 (LAN_CLKREQ#) configured by FSP
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PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD1_RST#
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PAD_NC(GPP_F21, NONE),
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PAD_NC(GPP_F22, NONE),
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PAD_NC(GPP_F23, NONE),
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/* ------- GPIO Group GPP_H ------- */
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PAD_NC(GPP_H0, NONE),
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PAD_NC(GPP_H1, NONE),
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PAD_NC(GPP_H2, NONE),
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PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // T_SDA (Touchpad)
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // T_SCL (Touchpad)
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (TBT)
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (TBT)
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PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
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// GPP_H10 (UART0_RX) configured in bootblock
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// GPP_H11 (UART0_TX) configured in bootblock
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PAD_NC(GPP_H12, NONE),
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PAD_NC(GPP_H13, NONE),
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// GPP_H14 missing
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PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
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// GPP_H16 missing
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PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
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PAD_NC(GPP_H19, NONE),
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PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PM_CLKRUN#
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PAD_NC(GPP_H21, NONE),
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PAD_NC(GPP_H22, NONE),
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// GPP_H23 (CARD_CLKREQ#) configured by FSP
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/* ------- GPIO Group GPP_R ------- */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_T ------- */
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
16
src/mainboard/system76/rpl/variants/galp7/gpio_early.c
Normal file
16
src/mainboard/system76/rpl/variants/galp7/gpio_early.c
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
26
src/mainboard/system76/rpl/variants/galp7/hda_verb.c
Normal file
26
src/mainboard/system76/rpl/variants/galp7/hda_verb.c
Normal file
@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC256 */
|
||||
0x10ec0256, /* Vendor ID */
|
||||
0x15584041, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15584041),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
78
src/mainboard/system76/rpl/variants/galp7/overridetree.cb
Normal file
78
src/mainboard/system76/rpl/variants/galp7/overridetree.cb
Normal file
@ -0,0 +1,78 @@
|
||||
chip soc/intel/alderlake
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x4041 inherit
|
||||
|
||||
device ref pcie4_0 on
|
||||
# PCIe PEG0 x4, Clock 0 (SSD1)
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_src = 0,
|
||||
.clk_req = 0,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref tbt_pcie_rp0 on end
|
||||
device ref tcss_xhci on
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
end
|
||||
device ref tcss_dma0 on end
|
||||
device ref xhci on
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 (USB 3.2 Gen1)
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 (USB 3.2 Gen2)
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 (USB 3.2 Gen1)
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 (Thunerbolt)
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2 (USB 3.2 Gen1)
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1 (USB 3.2 Gen1)
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 (USB 3.2 Gen2)
|
||||
end
|
||||
device ref i2c0 on
|
||||
# Touchpad I2C bus
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN0412""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""FTCS1000""
|
||||
register "generic.desc" = ""FocalTech Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 38 on end
|
||||
end
|
||||
end
|
||||
device ref sata off end
|
||||
device ref pcie_rp5 on
|
||||
# PCIe RP#5 x1, Clock 2 (WLAN)
|
||||
register "pch_pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe RP#9 x1, Clock 5 (CARD)
|
||||
register "pch_pcie_rp[PCH_RP(9)]" = "{
|
||||
.clk_src = 5,
|
||||
.clk_req = 5,
|
||||
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp10 on
|
||||
# PCIe RP#10 x1, Clock 6 (GLAN)
|
||||
register "pch_pcie_rp[PCH_RP(10)]" = "{
|
||||
.clk_src = 6,
|
||||
.clk_req = 6,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
end
|
||||
end
|
||||
25
src/mainboard/system76/rpl/variants/galp7/romstage.c
Normal file
25
src/mainboard/system76/rpl/variants/galp7/romstage.c
Normal file
@ -0,0 +1,25 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR4,
|
||||
};
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
|
||||
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||
mupd->FspmConfig.GpioOverride = 0;
|
||||
|
||||
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
Reference in New Issue
Block a user