Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -323,15 +323,14 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
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/**
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* i945 supports two DIMMs, in two configurations:
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*
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* - single channel with two dimms
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* - dual channel with one dimm per channel
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* - single channel with two DIMMs
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* - dual channel with one DIMM per channel
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*
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* In practice dual channel mainboards have their spd at 0x50, 0x52
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* whereas single channel configurations have their spd at 0x50/x51
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* In practice dual channel mainboards have their SPD at 0x50/0x52
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* whereas single channel configurations have their SPD at 0x50/0x51.
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*
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* The capability register knows a lot about the channel configuration
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* but for now we stick with the information we gather from the SPD
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* ROMs
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* but for now we stick with the information we gather via SPD.
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*/
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if (sdram_capabilities_dual_channel()) {
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@@ -362,7 +361,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
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*/
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for (i=0; i<(2 * DIMM_SOCKETS); i++) {
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u8 reg8, device = DIMM_SPD_BASE + i;
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u8 reg8, device = DIMM0 + i;
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/* Initialize the socket information with a sane value */
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sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
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@@ -453,7 +452,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo)
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continue;
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/* Is the current DIMM a stacked DIMM? */
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if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
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if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
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sysinfo->package = 1;
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}
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}
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@@ -470,7 +469,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
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cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
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cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
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}
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if(!cas_mask) {
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@@ -531,7 +530,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
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continue;
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}
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current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
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current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES);
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while (current_cas_mask) {
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int highest_supported_cas = 0, current_cas = 0;
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@@ -553,11 +552,11 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
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idx = highest_supported_cas - current_cas;
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PRINTK_DEBUG("idx=%d, ", idx);
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PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
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PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
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PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]));
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PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]));
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if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
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spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
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if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
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spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
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PRINTK_DEBUG(": OK\n");
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break;
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}
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@@ -621,7 +620,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
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reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
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if (!reg8) {
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die("Invalid tRAS value.\n");
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}
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@@ -661,7 +660,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
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reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME);
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if (!reg8) {
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die("Invalid tRP value.\n");
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}
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@@ -702,7 +701,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
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reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY);
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if (!reg8) {
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die("Invalid tRCD value.\n");
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}
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@@ -742,7 +741,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
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reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME);
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if (!reg8) {
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die("Invalid tWR value.\n");
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}
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@@ -823,7 +822,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
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refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7);
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/* 15.6us */
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if (!refresh)
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@@ -851,7 +850,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo)
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
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if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
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die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
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}
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}
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@@ -1471,9 +1470,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
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sz = sdram_get_dimm_size(DIMM0 + i);
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sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
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sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */
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if (sz.side1 < 30)
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die("DDR-II rank size smaller than 128MB is not supported.\n");
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@@ -1565,7 +1564,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
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continue;
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}
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device = DIMM_SPD_BASE + i;
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device = DIMM0 + i;
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value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
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columnsrows = (value & 0x0f);
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