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mb/google/fizz: revise LED0 behavior for link speed 100Mb

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This patch revises LED0 Green light behavior from patch 2ecf3f8c.
For 100Mb link speed, LED0 should be OFF.

BUG=b:65437780, b:68284778, b:69950854, b:65808944
BRANCH=None
TEST=Run DUT with 100Mb and 1000Mb ethernet connection and observe
     LED0 is behaving as expected.

Change-Id: Ia805c955711b8ce77eba087a28427a005c456fa1
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22964
Reviewed-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Gaggery Tsai 2017-12-20 13:12:57 +08:00 committed by Martin Roth
parent 1df6bc69fb
commit d7de7bc1ee
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/fizz/devicetree.cb
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@ -306,7 +306,7 @@ chip soc/intel/skylake
device pci 19.2 off end # I2C #4 device pci 19.2 off end # I2C #4
device pci 1c.0 on # PCI Express Port 1 device pci 1c.0 on # PCI Express Port 1
chip drivers/net chip drivers/net
register "customized_leds" = "0x0fa7" register "customized_leds" = "0x0fa5"
register "wake" = "GPE0_PCI_EXP" register "wake" = "GPE0_PCI_EXP"
device pci 00.0 on end device pci 00.0 on end
end end
@ -326,7 +326,7 @@ chip soc/intel/skylake
device pci 1c.7 off end # PCI Express Port 8 device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on # PCI Express Port 9 for 2nd LAN device pci 1d.0 on # PCI Express Port 9 for 2nd LAN
chip drivers/net chip drivers/net
register "customized_leds" = "0x0fa7" register "customized_leds" = "0x0fa5"
device pci 00.0 on end device pci 00.0 on end
end end
end # PCI Express Port 9 for BtoB end # PCI Express Port 9 for BtoB