From d811be0127e74ef7931816c667c846afdb33ed19 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Wed, 14 Oct 2020 20:13:50 -0600
Subject: [PATCH] Fix ROM stage

Change-Id: Iede1a99d7a40e236c8cf9a89f652e23adb2289ed
---
 src/mainboard/system76/galp5/romstage.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/system76/galp5/romstage.c b/src/mainboard/system76/galp5/romstage.c
index 5c2d0f3aa2..90139a36f6 100644
--- a/src/mainboard/system76/galp5/romstage.c
+++ b/src/mainboard/system76/galp5/romstage.c
@@ -6,19 +6,10 @@
 
 //TODO: verify values
 static const struct mb_ddr4_cfg board_cfg = {
-	.dq_map[0] = {
-		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
-		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
-	},
-	.dq_map[1] = {
-		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
-		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
-	},
+	// dq_map unused on DDR4
+	// dqs_map unused on DDR4
 
-	.dqs_map[0] = {7, 6, 5, 4, 1, 0, 3, 2},
-	.dqs_map[1] = {5, 4, 7, 6, 1, 0, 3, 2},
-
-	.dq_pins_interleaved = 1,
+	.dq_pins_interleaved = 0,
 
 	.ect = 0,
 };