This goes a surprisingly long way to building the epia-n. It also has
important corrections to the Kconfig and Makefile.inc that were there. I would like to go ahead and get this in, because I don't want anyone to continue using what is in the upstream tree as it now exists. I also tested old-style build with this and it did not break anything. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
b203c2f95e
commit
d82e12858f
@ -1,2 +1,3 @@
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#subdirs-y += model_c7
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subdirs-$(CONFIG_CPU_VIA_C7) += model_c7
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subdirs-y += model_c7
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subdirs-$(CONFIG_CPU_VIA_C3) += model_c3
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3
src/cpu/via/model_c3/Kconfig
Normal file
3
src/cpu/via/model_c3/Kconfig
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@ -0,0 +1,3 @@
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config CPU_VIA_C3
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bool
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default n
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11
src/cpu/via/model_c3/Makefile.inc
Normal file
11
src/cpu/via/model_c3/Makefile.inc
Normal file
@ -0,0 +1,11 @@
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/fpu
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subdirs-y += ../../x86/mmx
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subdirs-y += ../../x86/sse
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../../intel/microcode
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obj-y += model_c3_init.o
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@ -1,4 +1,3 @@
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ifeq ($(CONFIG_CPU_VIA_C7),y)
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/mtrr
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subdirs-y += ../../x86/fpu
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subdirs-y += ../../x86/fpu
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@ -8,6 +7,5 @@ ifeq ($(CONFIG_CPU_VIA_C7),y)
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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subdirs-y += ../../x86/smm
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subdirs-y += ../../intel/microcode
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subdirs-y += ../../intel/microcode
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endif
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obj-y += model_c7_init.o
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obj-y += model_c7_init.o
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@ -2,36 +2,9 @@ choice
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prompt "Mainboard model"
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prompt "Mainboard model"
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depends on VENDOR_VIA
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depends on VENDOR_VIA
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config BOARD_VIA_VT8454C
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source "src/mainboard/via/vt8454c/Kconfig"
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bool "vt8454c"
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source "src/mainboard/via/epia-n/Kconfig"
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select ARCH_X86
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select CPU_VIA_C7
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select NORTHBRIDGE_VIA_CX700
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# select SOUTHBRIDGE_INTEL_I82801GX
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select SUPERIO_VIA_VT1211
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select PIRQ_TABLE
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# select MMCONF_SUPPORT
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select USE_PRINTK_IN_CAR
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help
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Kontron 986LCD-M Series mainboards
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endchoice
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endchoice
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config MAINBOARD_DIR
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string
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default via/vt8454c
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depends on BOARD_VIA_VT8454C
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config DCACHE_RAM_BASE
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hex
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default 0xffef0000
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depends on BOARD_VIA_VT8454C
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_VIA_VT8454C
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config MAINBOARD_PART_NUMBER
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string
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default "VT8454C"
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depends on BOARD_VIA_VT8454C
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37
src/mainboard/via/epia-n/Kconfig
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37
src/mainboard/via/epia-n/Kconfig
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config BOARD_VIA_EPIA_N
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bool "via epia-n"
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select ARCH_X86
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select CPU_VIA_C3
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select NORTHBRIDGE_VIA_CN400
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select SOUTHBRIDGE_VIA_VT8237R
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select SUPERIO_WINBOND_W83697HF
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select PIRQ_TABLE
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select USE_PRINTK_IN_CAR
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help
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VIA Epia-n mainboards
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config MAINBOARD_DIR
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string
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default via/epia-n
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depends on BOARD_VIA_EPIA_N
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#config DCACHE_RAM_BASE
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# hex
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# default 0xffef0000
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# depends on BOARD_VIA_EPIA_N
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#
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#config DCACHE_RAM_SIZE
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# hex
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# default 0x8000
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# depends on BOARD_VIA_EPIA_N
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config MAINBOARD_PART_NUMBER
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string
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default "EPIA_N"
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depends on BOARD_VIA_EPIA_N
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config VIDEO_MB
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int
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default 32
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depends on BOARD_VIA_EPIA_N
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64
src/mainboard/via/epia-n/Makefile.inc
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64
src/mainboard/via/epia-n/Makefile.inc
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@ -0,0 +1,64 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 VIA Technologies, Inc.
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## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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initobj-y += crt0.o
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obj-y += mainboard.o
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obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
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obj-$(CONFIG_HAVE_MP_TABLE) += object mptable.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
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crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
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crt0-y += auto.inc
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crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
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ifdef POST_EVALUATION
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MAINBOARD_OPTIONS=\
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-DCONFIG_USE_PRINTK_IN_CAR=1 \
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-DCONFIG_HAVE_HIGH_TABLES=1
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$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
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$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
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iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
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mv dsdt.hex $@
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$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
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perl -e 's/\.rodata/.rom.data/g' -pi $@
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perl -e 's/\.text/.section .rom.text/g' -pi $@
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endif
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101
src/mainboard/via/epia-n/devicetree.cb
Normal file
101
src/mainboard/via/epia-n/devicetree.cb
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@ -0,0 +1,101 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 VIA Technologies, Inc.
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## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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chip northbridge/via/cn400 # Northbridge
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device apic_cluster 0 on # APIC cluster
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chip cpu/via/model_c3 # VIA C3
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # AGP Bridge
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device pci 0.1 on end # Error Reporting
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device pci 0.2 on end # Host Bus Control
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device pci 0.3 on end # Memory Controller
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device pci 0.4 on end # Power Management
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device pci 0.7 on end # V-Link Controller
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device pci 1.0 on end # PCI Bridge
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chip southbridge/via/vt8237r # Southbridge
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# Enable both IDE channels.
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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# Both cables are 40pin.
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register "ide0_80pin_cable" = "0"
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register "ide1_80pin_cable" = "0"
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device pci f.0 on end # IDE/SATA
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device pci f.1 on end # IDE
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register "fn_ctrl_lo" = "0xC0" # Disable AC/MC97
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register "fn_ctrl_hi" = "0x9d" # Disable USB Direct & LAN Gating
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device pci 10.0 on end # OHCI
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device pci 10.1 on end # OHCI
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device pci 10.2 on end # OHCI
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device pci 10.3 on end # OHCI
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device pci 10.4 on end # EHCI
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device pci 10.5 off end # USB Direct
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device pci 11.0 on # Southbridge LPC
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chip superio/winbond/w83697hf # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.6 off # IR Port
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io 0x60 = 0x000
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end
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device pnp 2e.7 off # GPIO 1
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io 0x60 = 0x201 # 0x201
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end
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device pnp 2e.8 off # GPIO 5
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io 0x60 = 0x330 # 0x330
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end
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device pnp 2e.9 off # GPIO 2, 3,and 4
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io 0x60 = 0x000 #
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end
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device pnp 2e.a off # ACPI
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io 0x60 = 0x000 #
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end
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device pnp 2e.b on # HWM
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io 0x60 = 0x290
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irq 0x70 = 0
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end
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end
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end
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device pci 11.5 off end # AC'97 audio
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device pci 11.6 off end # AC'97 Modem
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device pci 12.0 on end # Ethernet
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end
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end
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end
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||||||
32
src/mainboard/via/vt8454c/Kconfig
Normal file
32
src/mainboard/via/vt8454c/Kconfig
Normal file
@ -0,0 +1,32 @@
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config BOARD_VIA_VT8454C
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bool "vt8454c"
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select ARCH_X86
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select CPU_VIA_C7
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select NORTHBRIDGE_VIA_CX700
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# select SOUTHBRIDGE_INTEL_I82801GX
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select SUPERIO_VIA_VT1211
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select PIRQ_TABLE
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# select MMCONF_SUPPORT
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select USE_PRINTK_IN_CAR
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help
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||||||
|
Kontron 986LCD-M Series mainboards
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||||||
|
|
||||||
|
config MAINBOARD_DIR
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||||||
|
string
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||||||
|
default via/vt8454c
|
||||||
|
depends on BOARD_VIA_VT8454C
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||||||
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|
||||||
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config DCACHE_RAM_BASE
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hex
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||||||
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default 0xffef0000
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||||||
|
depends on BOARD_VIA_VT8454C
|
||||||
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|
||||||
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config DCACHE_RAM_SIZE
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hex
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||||||
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default 0x8000
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||||||
|
depends on BOARD_VIA_VT8454C
|
||||||
|
|
||||||
|
config MAINBOARD_PART_NUMBER
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string
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default "VT8454C"
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||||||
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depends on BOARD_VIA_VT8454C
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||||||
@ -1,5 +1,6 @@
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|||||||
#source src/northbridge/via/cn700/Kconfig
|
#source src/northbridge/via/cn700/Kconfig
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source src/northbridge/via/cx700/Kconfig
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source src/northbridge/via/cx700/Kconfig
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source src/northbridge/via/cn400/Kconfig
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#source src/northbridge/via/vt8601/Kconfig
|
#source src/northbridge/via/vt8601/Kconfig
|
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#source src/northbridge/via/vt8623/Kconfig
|
#source src/northbridge/via/vt8623/Kconfig
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||||||
#source src/northbridge/via/vx800/Kconfig
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#source src/northbridge/via/vx800/Kconfig
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@ -19,7 +19,7 @@
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*/
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*/
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#ifndef __ROMCC__
|
#ifndef __ROMCC__
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||||||
static void cn400_noop()
|
static void cn400_noop(void)
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{
|
{
|
||||||
}
|
}
|
||||||
#endif
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#endif
|
||||||
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|||||||
Loading…
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Reference in New Issue
Block a user