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soc/intel/common: Enable decoding of the COMB range to LPC based on Kconfig

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By default all Intel platform has enable IO decode range for COMA if
CONFIG_DRIVERS_UART_8250IO is selected.

With this patch, COMB will get enable based on
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE Kconfig selection.

Also make lpc_enable_fixed_io_ranges() function returns Enabled I/O bits to avoid
an additional pci configuration read to get the same data.

Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Subrata Banik
2018-03-08 14:04:52 +05:30
committed by Martin Roth
parent 80edc84687
commit d83faceefa
3 changed files with 30 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/common/block/include/intelblocks/lpc_lib.h
View File

@@ -59,8 +59,11 @@ struct lpc_mmio_range {
size_t size; size_t size;
}; };
/* Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together. */ /*
void lpc_enable_fixed_io_ranges(uint16_t io_enables); * Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together.
* Output:I/O Enable Bits
*/
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables);
/* Open a generic IO window to the LPC bus. Four windows are available. */ /* Open a generic IO window to the LPC bus. Four windows are available. */
void lpc_open_pmio_window(uint16_t base, uint16_t size); void lpc_open_pmio_window(uint16_t base, uint16_t size);
/* Close all generic IO windows to the LPC bus. */ /* Close all generic IO windows to the LPC bus. */

8
src/soc/intel/common/block/lpc/Kconfig
View File

@@ -3,3 +3,11 @@ config SOC_INTEL_COMMON_BLOCK_LPC
help help
Use common LPC code for platform. Only soc specific code needs to Use common LPC code for platform. Only soc specific code needs to
be implemented as per requirement. be implemented as per requirement.
config SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
depends on SOC_INTEL_COMMON_BLOCK_LPC && DRIVERS_UART_8250IO
bool
default n
help
By default COMA range to LPC is enable. COMB range to LPC is optional
and should select based on platform dedicated selection.

27
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2016 Intel Corp. * Copyright (C) 2016-2018 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
@@ -25,13 +25,15 @@
#include "lpc_def.h" #include "lpc_def.h"
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
void lpc_enable_fixed_io_ranges(uint16_t io_enables) uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
{ {
uint16_t reg_io_enables; uint16_t reg_io_enables;
reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES);
io_enables |= reg_io_enables; io_enables |= reg_io_enables;
pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables);
return io_enables;
} }
/* /*
@@ -225,15 +227,20 @@ void lpc_set_serirq_mode(enum serirq_mode mode)
void lpc_io_setup_comm_a_b(void) void lpc_io_setup_comm_a_b(void)
{ {
/* /* ComA Range 3F8h-3FFh [2:0] */
* Setup I/O Decode Range Register for LPC uint16_t com_ranges = LPC_IOD_COMA_RANGE;
* ComA Range 3F8h-3FFh [2:0] uint16_t com_enable = LPC_IOE_COMA_EN;
* ComB Range 2F8h-2FFh [6:4]
*/ /* ComB Range 2F8h-2FFh [6:4] */
pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE)) {
LPC_IOD_COMA_RANGE | LPC_IOD_COMB_RANGE); com_ranges |= LPC_IOD_COMB_RANGE;
com_enable |= LPC_IOE_COMB_EN;
}
/* Setup I/O Decode Range Register for LPC */
pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);
/* Enable ComA and ComB Port */ /* Enable ComA and ComB Port */
lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN); lpc_enable_fixed_io_ranges(com_enable);
} }
static void lpc_set_gen_decode_range( static void lpc_set_gen_decode_range(