nb/intel/gm45: Fix panel-power-sequence clock divisor

We kept this value at it's default on the native graphics init path.
Maybe the Video BIOS path, too, I don't know if the VBIOS sets it.

The panel power sequencer uses the core display clock (CDCLK). It's
based on the HPLLVCO and a frequency selection we made during raminit.
The value written is the (actual divisor/2)-1 for a 100us timer.

v2: Fix unaligned mmio access inherited from Linux.

v3: Use MCHBAR8() instead. Also, the unaligned access might have
    worked after all.

Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17619
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/gm45/raminit.c

@@ -749,7 +749,7 @@ static void set_system_memory_frequency(const timings_t *const timings)
 
 int raminit_read_vco_index(void)
 {
-	switch (MCHBAR8(0x0c0f) & 0x7) {
+	switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) {
 	case VCO_2666:
 		return 0;
 	case VCO_3200: