From d892a336bbf6678adb83a5b6f48f13dea64f45eb Mon Sep 17 00:00:00 2001
From: zhourui <zhourui@huaqin.corp-partner.google.com>
Date: Mon, 21 Nov 2022 14:44:39 +0800
Subject: [PATCH] mb/google/dedede/variants/sasukette: Disable PCIE RP8 and
 CLKSRC4

This change disables unused PCIE RP8 and CLKSRC4. Without this change
sasukette cannot enter into s0ix properly.

BUG=b:259891452
TEST=Build and verified in sasukette

Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 .../google/dedede/variants/sasukette/overridetree.cb          | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
index 1cda193268..43a68dbb16 100644
--- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb
@@ -8,6 +8,10 @@ fw_config
 end
 
 chip soc/intel/jasperlake
+	# Disable PCIe Root Port 8 (index 7)
+	register "PcieRpEnable[7]" = "0"
+	# Disable PCIe Clock Source 4 (index 3)
+	register "PcieClkSrcUsage[3]" = "0xff"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+