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drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD

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As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.

To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/rtc/rtc-mc146818-lib.c?id=3ae8fd4157

BUG=b:346716300
TEST=none
BRANCH=skyrim

Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Yu-Ping Wu
2024-07-18 14:41:49 +08:00
committed by Yu-Ping Wu
parent 9b2d995bdb
commit d8bed2d001
2 changed files with 5 additions and 0 deletions
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3
src/drivers/pc80/rtc/mc146818rtc.c
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@@ -65,6 +65,9 @@ int cmos_error(void)
#define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_CONTROL_DEFAULT (RTC_24H)
#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
_Static_assert(!CONFIG(SOC_AMD_COMMON) || !(RTC_FREQ_SELECT_DEFAULT & RTC_AMD_BANK_SELECT),
"Bank 1 should not be selected for AMD");
static bool __cmos_init(bool invalid) static bool __cmos_init(bool invalid)
{ {
bool cmos_invalid; bool cmos_invalid;

2
src/include/pc80/mc146818rtc.h
View File

@@ -33,6 +33,8 @@
# define RTC_REF_CLCK_4MHZ 0x00 # define RTC_REF_CLCK_4MHZ 0x00
# define RTC_REF_CLCK_1MHZ 0x10 # define RTC_REF_CLCK_1MHZ 0x10
# define RTC_REF_CLCK_32KHZ 0x20 # define RTC_REF_CLCK_32KHZ 0x20
/* In AMD BKDG, bit 4 is DV0 bank selection. Bits 5 and 6 are reserved. */
# define RTC_AMD_BANK_SELECT 0x10
/* 2 values for divider stage reset, others for "testing purposes only" */ /* 2 values for divider stage reset, others for "testing purposes only" */
# define RTC_DIV_RESET1 0x60 # define RTC_DIV_RESET1 0x60
# define RTC_DIV_RESET2 0x70 # define RTC_DIV_RESET2 0x70