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driver/intel/fsp1_1: Fix boot failure for non-verstage case

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Currently car_stage_entry is defined only in romstage_after_verstage and
as a result when SEPARATE_VERSTAGE is not selected, there is no
entry point into romstage and romstage will not be started at all.

The solution is move out romstage_after_verstage.S from fsp1.1 driver
to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the
build and boot issue with this change.

Besides that, rename the romstage_after_verstage to romstage_c_entry
in more appropriate naming convention after this fix.

Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0),
romstage can be started successfully.

Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/17976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Teo Boon Tiong
2016-12-28 18:56:26 +08:00
committed by Aaron Durbin
parent 951ec96f17
commit d8e34b2c44
5 changed files with 8 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/drivers/intel/fsp1_1/Makefile.inc
View File

@@ -28,7 +28,6 @@ romstage-y += fsp_util.c
romstage-y += hob.c
romstage-y += raminit.c
romstage-y += romstage.c
romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
romstage-y += stack.c
romstage-y += stage_cache.c
romstage-$(CONFIG_MMA) += mma_core.c

2
src/drivers/intel/fsp1_1/car.c
View File

@@ -68,7 +68,7 @@ asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
}
/* Entry point taken when romstage is called after a separate verstage. */
asmlinkage void *romstage_after_verstage(void)
asmlinkage void *romstage_c_entry(void)
{
/* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
* is still enabled. We can directly access work buffer here. */

2
src/drivers/intel/fsp1_1/include/fsp/car.h
View File

@@ -32,7 +32,7 @@ struct cache_as_ram_params {
/* Entry points from the cache-as-ram assembly code. */
asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params);
asmlinkage void after_cache_as_ram(void *chipset_context);
asmlinkage void *romstage_after_verstage(void);
asmlinkage void *romstage_c_entry(void);
/* Per stage calls from the above two functions. The void * return from
* cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */

38
src/drivers/intel/fsp1_1/romstage_after_verstage.S
View File

@@ -1,38 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
.text
.global car_stage_entry
car_stage_entry:
call romstage_after_verstage
#include "after_raminit.S"
movb $0x69, %ah
jmp .Lhlt
.Lhlt:
xchg %al, %ah
#if IS_ENABLED(CONFIG_POST_IO)
outb %al, $CONFIG_POST_IO_PORT
#else
post_code(POST_DEAD_CODE)
#endif
movl $LHLT_DELAY, %ecx
.Lhlt_Delay:
outb %al, $0xED
loop .Lhlt_Delay
jmp .Lhlt