soc/intel/braswell: Fix most of the issues detected by checkpatch

Fix the following errors and warnings detected by checkpatch.pl:

ERROR: that open brace { should be on the previous line
ERROR: return is not a function, parentheses are not required
WARNING: braces {} are not necessary for any arm of this statement
WARNING: line over 80 characters
WARNING: braces {} are not necessary for single statement blocks
WARNING: Avoid unnecessary line continuations
WARNING: break is not useful after a goto or return
WARNING: else is not generally useful after a break or return

False positives are generated by checkpatch for the following test:
ERROR: Macros with complex values should be enclosed in parentheses

TEST=Build for cyan

Change-Id: I19048895145b138a63100b29f829ff446ff71b58
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18871
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)

src/soc/intel/braswell/acpi.c

@@ -525,12 +525,10 @@ void southcluster_inject_dsdt(device_t device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* Fill in the Wifi Region id */
-		if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN)) {
+		if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN))
 			gnvs->cid1 = wifi_regulatory_domain();
-		} else {
+		else
-
 			gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
-		}
 		acpi_save_gnvs((unsigned long)gnvs);
 		/* And tell SMI about it */
 		smm_setup_structures(gnvs, NULL, NULL);

src/soc/intel/braswell/chip.h

@@ -58,7 +58,7 @@ struct soc_intel_braswell_config {
 	int disable_slp_x_stretch_sus_fail;
 
 	/* LPE Audio Clock configuration. */
-	enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */
+	enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz */
 
 	/* Native SD Card controller - override controller capabilities. */
 	uint32_t sdcard_cap_low;

src/soc/intel/braswell/cpu.c

@@ -229,7 +229,6 @@ void soc_init_cpus(device_t dev)
 	printk(BIOS_SPEW, "%s/%s ( %s )\n",
 			__FILE__, __func__, dev_name(dev));
 
-	if (mp_init_with_smm(cpu_bus, &mp_ops)) {
+	if (mp_init_with_smm(cpu_bus, &mp_ops))
 		printk(BIOS_ERR, "MP initialization failure.\n");
 }
-}

src/soc/intel/braswell/lpe.c

@@ -142,9 +142,9 @@ static void lpe_stash_firmware_info(device_t dev)
 
 	/* Also put the address in MMIO space like on C0 BTM */
 	mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
-	write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), \
+	write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),
 		res->base);
-	write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), \
+	write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0),
 		res->size);
 }
 

src/soc/intel/braswell/southcluster.c

@@ -390,7 +390,6 @@ static int place_device_in_d3hot(device_t dev)
 	DEV_CASE(TXE) :
 		/* TXE cannot be placed in D3Hot. */
 		return 0;
-		break;
 	DEV_CASE(PCIE_PORT1) :
 	DEV_CASE(PCIE_PORT2) :
 	DEV_CASE(PCIE_PORT3) :

src/soc/intel/braswell/spi.c

@@ -350,7 +350,8 @@ static int spi_setup_opcode(spi_transaction *trans)
 		optypes = (optypes & 0xfffc) | (trans->type & 0x3);
 		writew_(optypes, cntlr.optype);
 		return 0;
-	} else {
+	}
+
 	/* The lock is on. See if what we need is on the menu. */
 	uint8_t optype;
 	uint16_t opcode_index;
@@ -387,7 +388,6 @@ static int spi_setup_opcode(spi_transaction *trans)
 	}
 	return opcode_index;
 }
-}
 
 static int spi_setup_offset(spi_transaction *trans)
 {

src/soc/intel/braswell/tsc_freq.c

@@ -41,10 +41,9 @@ static const unsigned int cpu_bus_clk_freq_table[] = {
 unsigned int cpu_bus_freq_khz(void)
 {
 	msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
-	if ((clk_info.lo & 0xF)  < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int)))
+	if ((clk_info.lo & 0xF)
-	{
+		< (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int)))
-		return(cpu_bus_clk_freq_table[clk_info.lo & 0xF]);
+		return cpu_bus_clk_freq_table[clk_info.lo & 0xF];
-	}
 	return 0;
 }
 

src/soc/intel/braswell/xhci.c

@@ -42,7 +42,8 @@ static void xhci_init(device_t dev)
 				config->usb_comp_bg),
 			REG_SCRIPT_END
 		};
-		printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg);
+		printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n",
+			config->usb_comp_bg);
 		reg_script_run(ops);
 	}
 }