acpi: Add PPTT support
This patch adds code to generate Processor Properties Topology Tables (PPTT) compliant to the ACPI 6.4 specification. - The 'acpi_get_pptt_topology' hook is mandatory once ACPI_PPTT is selected. Its purpose is to return a pointer to a topology tree, which describes the relationship between CPUs and caches. The hook can be provided by, for example, mainboard code. Background: We are currently working on mainboard code for qemu-sbsa and Neoverse N2. Both require a valid PPTT table. Patch was tested against the qemu-sbsa board. Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Lean Sheng Tan
parent
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d982274a4e
@@ -91,3 +91,17 @@ config MAX_ACPI_TABLE_SIZE_KB
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default 144
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help
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Set the maximum size of all ACPI tables in KiB.
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config ACPI_PPTT
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bool
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depends on HAVE_ACPI_TABLES
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help
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Selected to build an ACPI Processor Properties Topology Table.
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config ACPI_PPTT_MAX_CACHES
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int
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depends on ACPI_PPTT
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default 4
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help
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This variable sets the maximum number of distinct caches per
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topology level. Increasing this option also increases stack usage.
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@@ -8,6 +8,7 @@ ramstage-y += acpi_apic.c
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ramstage-y += acpi_dmar.c
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ramstage-y += acpi_hpet.c
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endif
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ramstage-$(CONFIG_ACPI_PPTT) += acpi_pptt.c
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ramstage-y += acpigen.c
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ramstage-y += acpigen_dptf.c
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ramstage-y += acpigen_dsm.c
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@@ -1204,6 +1204,18 @@ unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t
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return lpi_desc->header.length;
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}
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static void acpi_create_pptt(acpi_header_t *header, void *unused)
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{
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if (!CONFIG(ACPI_PPTT))
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return;
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if (acpi_fill_header(header, "PPTT", PPTT, sizeof(acpi_pptt_t)) != CB_SUCCESS)
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return;
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acpi_pptt_t *pptt = (acpi_pptt_t *)header;
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acpi_create_pptt_body(pptt);
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}
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static uint8_t acpi_spcr_type(void)
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{
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/* 16550-compatible with parameters defined in Generic Address Structure */
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@@ -1394,6 +1406,7 @@ unsigned long write_acpi_tables(const unsigned long start)
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{ acpi_create_bert, NULL, sizeof(acpi_bert_t) },
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{ acpi_create_spcr, NULL, sizeof(acpi_spcr_t) },
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{ acpi_create_gtdt, NULL, sizeof(acpi_gtdt_t) },
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{ acpi_create_pptt, NULL, sizeof(acpi_pptt_t) },
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};
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current = start;
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@@ -1743,6 +1756,8 @@ int get_acpi_table_revision(enum acpi_tables table)
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return 4;
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case GTDT:
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return 3;
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case PPTT: /* ACPI 6.4 */
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return 3;
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default:
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return -1;
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}
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186
src/acpi/acpi_pptt.c
Normal file
186
src/acpi/acpi_pptt.c
Normal file
@@ -0,0 +1,186 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <include/assert.h>
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#include <console/console.h>
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/*
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* A structure to hold a cache pointer
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* and its corresponding reference within
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* the PPTT table.
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*/
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struct cache_reference {
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struct pptt_cache *cache; // cache pointer
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u32 ref; // and its reference within PPTT
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};
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/*
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* A list of 'struct cache_reference', used
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* to keep track of generated caches per topology level.
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*/
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struct cache_list {
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u32 n_caches; // number of caches in list
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struct cache_reference cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; // cache reference list
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};
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/*
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* Start of the PPTT table. Constant
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* value as soon as we enter acpi_create_pptt_body.
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*/
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static uintptr_t pptt_start;
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/* --- Helper Functions (non exposed) --- */
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static inline u32 node_to_reference(const void *node)
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{
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/*
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* References are the offset from the start
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* of the PPTT table.
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*
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* PPTT
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* +---------+ <- pptt_start (acpi_pptt_t) <---+
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* | | | node - pptt_start
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* | | |
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* +---------+ <- node (cpu or cache) <--------+
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* | |
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* | |
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* | |
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* +---------+
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*/
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return ((uintptr_t)node - pptt_start);
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}
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static u32 count_resources(struct pptt_cpu_resources *res)
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{
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u32 n_resources = 0;
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while (res != NULL) {
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n_resources += 1;
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res = res->next;
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}
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return n_resources;
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}
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static u32 cache_list_ref_of(struct cache_list *cache_list, const struct pptt_cache *cache)
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{
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/*
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* Lookup the PPTT reference of 'cache'.
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* Return 0, if no PPTT structure exists for 'cache'.
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*/
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for (int i = 0; i < cache_list->n_caches; i++) {
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if (cache_list->cache_refs[i].cache == cache)
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return cache_list->cache_refs[i].ref;
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}
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/* no cache reference found */
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return 0;
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}
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static inline void cache_list_append(struct cache_list *cache_list, struct pptt_cache *cache, const u32 ref)
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{
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printk(BIOS_DEBUG, "acpi: pptt: cache=%p ref=%u\n", cache, ref);
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cache_list->cache_refs[cache_list->n_caches].cache = cache;
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cache_list->cache_refs[cache_list->n_caches].ref = ref;
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cache_list->n_caches += 1;
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}
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static u32 new_pptt_cache(unsigned long *current, struct pptt_cache *cache, struct cache_list *cache_list)
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{
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static u32 unique_cache_id = 1;
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u32 current_reference = 0;
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if ((current_reference = cache_list_ref_of(cache_list, cache)) != 0)
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return current_reference;
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if (cache_list->n_caches >= CONFIG_ACPI_PPTT_MAX_CACHES) {
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printk(BIOS_WARNING, "acpi: pptt: Too many distinct caches! PPTT incomplete.\n");
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return 0;
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}
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acpi_pptt_cache_node_t *cache_node = (acpi_pptt_cache_node_t *)*current;
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memset(cache_node, 0x0, sizeof(acpi_pptt_cache_node_t));
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cache_node->type = PPTT_NODE_TYPE_CACHE;
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cache_node->length = sizeof(acpi_pptt_cache_node_t);
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cache_node->flags = cache->flags.raw;
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cache_node->size = cache->size;
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cache_node->n_sets = cache->numsets;
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cache_node->associativity = cache->associativity;
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cache_node->attributes = cache->attributes;
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cache_node->line_size = cache->line_size;
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cache_node->cache_id = unique_cache_id++;
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*current += cache_node->length;
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current_reference = node_to_reference(cache_node);
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cache_list_append(cache_list, cache, current_reference);
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if (cache->next_level != NULL)
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cache_node->next_level = new_pptt_cache(current, cache->next_level, cache_list);
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return current_reference;
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}
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static u32 new_pptt_cpu(unsigned long *current, const struct pptt_topology *cpu, const u32 parent_ref, struct cache_list *cache_list)
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{
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acpi_pptt_cpu_node_t *cpu_node = (acpi_pptt_cpu_node_t *)*current;
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const u32 n_resources = count_resources(cpu->resources);
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const u32 structure_length = sizeof(acpi_pptt_cpu_node_t) + (n_resources * sizeof(u32));
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memset(cpu_node, 0x0, structure_length);
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cpu_node->type = PPTT_NODE_TYPE_CPU;
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cpu_node->length = structure_length;
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cpu_node->flags = cpu->flags.raw;
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cpu_node->processor_id = cpu->processor_id;
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cpu_node->parent = parent_ref;
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*current += cpu_node->length;
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for (struct pptt_cpu_resources *it = cpu->resources; it != NULL; it = it->next)
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cpu_node->resources[cpu_node->n_resources++] = new_pptt_cache(current, it->cache, cache_list);
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return node_to_reference(cpu_node);
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}
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static void setup_topology(const struct pptt_topology *node, const u32 parent_ref, unsigned long *current)
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{
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struct cache_list cache_list = {
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.cache_refs = { },
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.n_caches = 0
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};
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while (node != NULL) {
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const u32 cpu_ref = new_pptt_cpu(current, node, parent_ref, &cache_list);
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setup_topology(node->child, cpu_ref, current);
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node = node->sibling;
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}
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}
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/* --- PPTT generation helper functions (exposed) --- */
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void acpi_create_pptt_body(acpi_pptt_t *pptt)
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{
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/* set start of pptt table */
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pptt_start = (uintptr_t)pptt;
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/* locate start of pptt body */
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unsigned long current = (unsigned long)(pptt->body);
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/* retrieve processor topology */
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const struct pptt_topology *topology_tree = acpi_get_pptt_topology();
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/* write processor properties topology table to memory */
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setup_topology(topology_tree, 0, ¤t);
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/* update length field in pptt header */
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pptt->header.length = current - (unsigned long)pptt;
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}
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