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mb/google/dedede: Create dita variant

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Create the dita variant of the taranza project by
copying the files to a new directory named for the variant.

BUG=b:317292413
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_DITA

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This commit is contained in:
Sheng-Liang Pan
2023-12-20 15:07:40 +08:00
committed by Felix Held
parent d968b8515c
commit d9dfd1f2fe
12 changed files with 524 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/google/dedede/Kconfig
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@@ -235,6 +235,13 @@ config BOARD_GOOGLE_DEXI
select RT8168_SET_LED_MODE select RT8168_SET_LED_MODE
select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
config BOARD_GOOGLE_DITA
select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD
select RT8168_SET_LED_MODE
select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
if BOARD_GOOGLE_BASEBOARD_DEDEDE if BOARD_GOOGLE_BASEBOARD_DEDEDE
config BASEBOARD_DEDEDE_LAPTOP config BASEBOARD_DEDEDE_LAPTOP
@@ -308,6 +315,7 @@ config MAINBOARD_PART_NUMBER
default "Taranza" if BOARD_GOOGLE_TARANZA default "Taranza" if BOARD_GOOGLE_TARANZA
default "Boxy" if BOARD_GOOGLE_BOXY default "Boxy" if BOARD_GOOGLE_BOXY
default "Dexi" if BOARD_GOOGLE_DEXI default "Dexi" if BOARD_GOOGLE_DEXI
default "Dita" if BOARD_GOOGLE_DITA
config MAX_CPUS config MAX_CPUS
int int
@@ -351,6 +359,7 @@ config VARIANT_DIR
default "taranza" if BOARD_GOOGLE_TARANZA default "taranza" if BOARD_GOOGLE_TARANZA
default "boxy" if BOARD_GOOGLE_BOXY default "boxy" if BOARD_GOOGLE_BOXY
default "dexi" if BOARD_GOOGLE_DEXI default "dexi" if BOARD_GOOGLE_DEXI
default "dita" if BOARD_GOOGLE_DITA
endif #BOARD_GOOGLE_BASEBOARD_DEDEDE endif #BOARD_GOOGLE_BASEBOARD_DEDEDE

3
src/mainboard/google/dedede/Kconfig.name
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@@ -94,3 +94,6 @@ config BOARD_GOOGLE_BOXY
config BOARD_GOOGLE_DEXI config BOARD_GOOGLE_DEXI
bool "-> Dexi" bool "-> Dexi"
config BOARD_GOOGLE_DITA
bool "-> Dita"

6
src/mainboard/google/dedede/variants/dita/Makefile.inc Normal file
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@@ -0,0 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-or-later
ramstage-y += gpio.c
ramstage-y += variant.c
ramstage-y += ramstage.c

108
src/mainboard/google/dedede/variants/dita/gpio.c Normal file
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@@ -0,0 +1,108 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* A11 : TOUCH_RPT_EN */
PAD_NC(GPP_A11, NONE),
/* A12 : USB_OC1_N */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
/* A13 : USB_OC2_N */
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
/* A14 : USB_OC3_N */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A18 : USB_OC0_N */
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* B9 : LAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* D2 : PWM_PP3300_BUZZER */
PAD_CFG_GPO(GPP_D2, 1, DEEP),
/* D4 : LAN_PE_ISOLATE_ODL_R */
PAD_CFG_GPO(GPP_D4, 1, DEEP),
/* D5 : TOUCH_RESET_L */
PAD_NC(GPP_D5, NONE),
/* D6 : EN_PP3300_TOUCH_S0 */
PAD_NC(GPP_D6, NONE),
/* D17 : LAN_PERST_L */
PAD_CFG_GPO(GPP_D17, 1, PLTRST),
/* D19 : WWAN_WLAN_COEX1 */
PAD_NC(GPP_D19, NONE),
/* D20 : WWAN_WLAN_COEX2 */
PAD_NC(GPP_D20, NONE),
/* E13 : GPP_E13/DDI0_DDC_SCL */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* E14 : GPP_E14/DDI0_DDC_SDA */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : GPP_E15/DDI1_DDC_SCL */
PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
/* E16 : GPP_E16/DDI1_DDC_SDA */
PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
/* G0 : SD_CMD */
PAD_NC(GPP_G0, NONE),
/* G1 : SD_DATA0 */
PAD_NC(GPP_G1, NONE),
/* G2 : SD_DATA1 */
PAD_NC(GPP_G2, NONE),
/* G3 : SD_DATA2 */
PAD_NC(GPP_G3, NONE),
/* G4 : SD_DATA3 */
PAD_NC(GPP_G4, NONE),
/* G5 : SD_CD_ODL */
PAD_NC(GPP_G5, NONE),
/* G6 : SD_CLK */
PAD_NC(GPP_G6, NONE),
/* G7 : SD_SDIO_WP */
PAD_NC(GPP_G7, NONE),
/* H4 : AP_I2C_TS_SDA */
PAD_NC(GPP_H4, NONE),
/* H5 : AP_I2C_TS_SCL */
PAD_NC(GPP_H5, NONE),
/* H6 : AP_I2C_CAM_SDA */
PAD_NC(GPP_H6, NONE),
/* H7 : AP_I2C_CAM_SCL */
PAD_NC(GPP_H7, NONE),
/* H15 : I2S_SPK_BCLK */
PAD_NC(GPP_H15, NONE),
/* R6 : I2S_SPK_LRCK */
PAD_NC(GPP_R6, NONE),
/* R7 : I2S_SPK_AUDIO */
PAD_NC(GPP_R7, NONE),
/* S2 : DMIC1_CLK */
PAD_NC(GPP_S2, NONE),
/* S3 : DMIC1_DATA */
PAD_NC(GPP_S3, NONE),
/* S6 : DMIC0_CLK */
PAD_NC(GPP_S6, NONE),
/* S7 : DMIC0_DATA */
PAD_NC(GPP_S7, NONE),
};
const struct pad_config *variant_override_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
static const gpio_t hpd_gpios[] = {
/* HDMI1 */
GPP_A17,
/* HDMI2 */
GPP_A16,
/* USB C0 */
GPP_B23,
};
const gpio_t *variant_hpd_gpios(size_t *num)
{
*num = ARRAY_SIZE(hpd_gpios);
return hpd_gpios;
}

8
src/mainboard/google/dedede/variants/dita/include/variant/ec.h Normal file
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@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <baseboard/dibbi/ec.h>
#endif

8
src/mainboard/google/dedede/variants/dita/include/variant/gpio.h Normal file
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@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <baseboard/gpio.h>
#endif /* MAINBOARD_GPIO_H */

8
src/mainboard/google/dedede/variants/dita/memory/Makefile.inc Normal file
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@@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/dita/memory/ src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt
SPD_SOURCES =
SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267
SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AB-MGCL, H54G56CYRBX247

11
src/mainboard/google/dedede/variants/dita/memory/dram_id.generated.txt Normal file
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@@ -0,0 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/dita/memory/ src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
K4U6E3S4AB-MGCL 0 (0000)
K4UBE3D4AB-MGCL 1 (0001)
H54G46CYRBX267 0 (0000)
H54G56CYRBX247 1 (0001)

16
src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt Normal file
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@@ -0,0 +1,16 @@
# This is a CSV file containing a list of memory parts used by this variant.
# One part per line with an optional fixed ID in column 2.
# Only include a fixed ID if it is required for legacy reasons!
# Generated IDs are dependent on the order of parts in this file,
# so new parts must always be added at the end of the file!
#
# Generate an updated Makefile.inc and dram_id.generated.txt by running the
# part_id_gen tool from util/spd_tools.
# See util/spd_tools/README.md for more details and instructions.
# Part Name
MT53E512M32D1NP-046 WT:B
K4U6E3S4AB-MGCL
K4UBE3D4AB-MGCL
H54G46CYRBX267
H54G56CYRBX247

304
src/mainboard/google/dedede/variants/dita/overridetree.cb Normal file
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@@ -0,0 +1,304 @@
chip soc/intel/jasperlake
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[4] = {
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 190,
.scl_hcnt = 100,
.sda_hold = 40,
}
},
}"
# Power limit config
register "power_limits_config[JSL_N4500_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 20,
.tdp_pl4 = 60,
}"
register "power_limits_config[JSL_N5100_6W_CORE]" = "{
.tdp_pl1_override = 6,
.tdp_pl2_override = 20,
.tdp_pl4 = 60,
}"
# Enable Root Port 3 (index 2) for LAN
# External PCIe port 7 is mapped to PCIe Root Port 3
register "PcieRpEnable[2]" = "1"
register "PcieClkSrcUsage[4]" = "2"
# Enable Root Port 7 (index 6) for WLAN
# External PCIe port 3 is mapped to PCIe Root Port 7
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[3]" = "6"
# Disable PCIe Root Port 8
register "PcieRpEnable[7]" = "0"
# Audio related configurations
register "PchHdaAudioLinkDmicEnable[0]" = "0"
register "PchHdaAudioLinkDmicEnable[1]" = "0"
# Disable SD card
register "sdcard_cd_gpio" = "0"
register "SdCardPowerEnableActiveHigh" = "0"
# Disable eDP on port A
register "DdiPortAConfig" = "0"
# Enable HPD and DDC for DDI port A
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "1"
# Does not support external vnn power rail
register "disable_external_bypass_vr" = "1"
# USB Port Configuration
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-C Port 0
register "usb2_ports[1]" = "{
.enable = 1,
.ocpin = OC1,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port A0
register "usb2_ports[2]" = "{
.enable = 1,
.ocpin = OC2,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port A1
register "usb2_ports[3]" = "{
.enable = 1,
.ocpin = OC3,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port A2
register "usb2_ports[4]" = "{
.enable = 1,
.ocpin = OC0,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port A3
register "usb2_ports[6]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port A4
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A4
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(7)"
register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
USB_PORT_WAKE_ENABLE(2) |
USB_PORT_WAKE_ENABLE(3) |
USB_PORT_WAKE_ENABLE(4) |
USB_PORT_WAKE_ENABLE(5) |
USB_PORT_WAKE_ENABLE(6)"
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000)
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN)
}"
register "controls.power_limits" = "{
.pl1 = {
.min_power = 3000,
.max_power = 6000,
.time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 100,
},
.pl2 = {
.min_power = 20000,
.max_power = 20000,
.time_window_min = 1 * MSECS_PER_SEC,
.time_window_max = 1 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
register "options.tsr[0].desc" = ""Memory""
register "options.tsr[1].desc" = ""Power""
register "options.tsr[2].desc" = ""Chassis""
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 3000 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
device generic 0 on end
end
end # SA Thermal device
device pci 14.0 on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 2.0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 2.1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 3)"
device usb 2.2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A2""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 3)"
device usb 2.3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A3""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 2.4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A4""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device usb 2.6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 3.0 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A4""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device usb 3.1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 3.2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 3)"
device usb 3.3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A3""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 3.4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A2""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 3)"
device usb 3.5 on end
end
end
end
end # USB xHCI
device pci 15.0 off end # I2C 0
device pci 15.1 off end # I2C 1
device pci 15.2 off end # I2C 2
device pci 15.3 off end # I2C 3
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""RTL5682""
register "name" = ""RT58""
register "desc" = ""Realtek RT5682""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
register "property_count" = "1"
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on end
end
end # I2C 4
device pci 1c.2 on
chip drivers/net
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW0_03" # GPP_B3
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
register "device_index" = "0"
device pci 00.0 on end
end
end # PCI Express Root Port 3 - RTL8111H LAN
device pci 1c.6 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW2_03"
device pci 00.0 on end
end
end # PCI Express Root Port 7 - WLAN
device pci 1c.7 off end # PCI Express Root Port 8
device pci 1f.3 on end # Intel HDA
end
end

35
src/mainboard/google/dedede/variants/dita/ramstage.c Normal file
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@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
/*
* Psys_pmax considerations
*
* Given the hardware design in dexi, the serial shunt resistor is 0.01ohm.
* The full scale of hardware PSYS signal 1.6v maps to system current 6.009A
* instead of real system power. The equation is shown below:
* PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x R631/(R631 + R638)
* R631/(R631 + R638) = 0.5325 = 36K / (36K + 31.6K)
*
* The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input
* current and the actual system power. Since there is no voltage information
* from PSYS, different voltage input would map to different Psys_pmax settings:
* For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W
* For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W
* For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W
*
* Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
* and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system
* power = 120W * 5A / 6.009A = 100W, which is the actual system power.
*/
const struct psys_config psys_config = {
.efficiency = 97,
.psys_imax_ma = 6009,
.bj_volts_mv = 19000,
.bj_power_w = 65,
};
void variant_devtree_update(void)
{
variant_update_psys_power_limits(&psys_config);
}

8
src/mainboard/google/dedede/variants/dita/variant.c Normal file
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@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <sar.h>
const char *get_wifi_sar_cbfs_filename(void)
{
return "wifi_sar-dexi.hex";
}