Fix for irq routing issues.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -69,7 +69,7 @@ default FALLBACK_SIZE = 512 * 1024
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default HAVE_PIRQ_TABLE = 1
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default HAVE_PIRQ_TABLE = 1
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default IRQ_SLOT_COUNT = 10
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default IRQ_SLOT_COUNT = 7
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default HAVE_MP_TABLE = 0
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default HAVE_MP_TABLE = 0
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default HAVE_ACPI_TABLES = 0
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default HAVE_ACPI_TABLES = 0
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default CONFIG_IOAPIC = 0
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default CONFIG_IOAPIC = 0
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@@ -23,7 +23,7 @@
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const struct irq_routing_table intel_irq_routing_table = {
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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PIRQ_VERSION, /* u16 version */
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32+16*IRQ_SLOT_COUNT, /* there can be total 10 devices on the bus */
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32+16*IRQ_SLOT_COUNT, /* there can be total 7 devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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0x00, /* Where the interrupt router lies (bus) */
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(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
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(0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0, /* IRQs devoted exclusively to PCI usage */
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@@ -31,19 +31,16 @@ const struct irq_routing_table intel_irq_routing_table = {
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0x24c0, /* Device */
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0x24c0, /* Device */
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0, /* Crap (miniport) */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x14, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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0xcd, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] USB UHCI Controller #1 */
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{0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] VGA compatible controller */
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{0x00,(0x1d<<3)|0x1, {{0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x01ef8}}, 0x0, 0x0}, /* [B] USB UHCI Controller #2 */
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{0x00,(0x1d<<3)|0x0, {{0x60, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x6b, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */
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{0x00,(0x1d<<3)|0x2, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x0, 0x0}, /* [C] USB UHCI Controller #3 */
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{0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x61, 0x1ef8}, {0x6b, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */
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{0x00,(0x1d<<3)|0x7, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x0, 0x0}, /* [D] USB2 EHCI Controller */
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{0x00,(0x1f<<3)|0x1, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] IDE Controller */
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{0x00,(0x1f<<3)|0x3, {{0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x01ef8}}, 0x0, 0x0}, /* [B] SMBus Controller */
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{0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x0, 0x0}, /* [A] VGA compatible controller */
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{0x00,(0x1f<<3)|0x5, {{0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x01ef8}}, 0x0, 0x0}, /* [B] AC'97 Audio Controller */
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{0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */
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{0x01,(0x08<<3)|0x0, {{0x68, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] Ethernet controller */
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{0x00,(0x1f<<3)|0x6, {{0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x64, 0x01ef8}}, 0x0, 0x0}, /* [B] AC'97 Modem Controller */
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{0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x01ef8}}, 0x1, 0x0}, /* [A] USB UHCI Controller #1 */
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{0x01,(0x01<<3)|0x0, {{0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x01ef8}}, 0x2, 0x0}, /* [B] USB UHCI Controller #2 */
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{0x01,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x01ef8}}, 0x3, 0x0}, /* [C] USB UHCI Controller #3 */
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}
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}
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};
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};
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