sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/dedede: Read DRAM population strap

Browse Source 
Configure DRAM population strap GPIO according to the schematics.
Configure an internal pull-up to support the boards in which the strap
is not populated. Read the strap and pass that information to FSP for
memory initialization.

BUG=b:152275658, b:154301008
TEST=Build and boot the mainboard. Ensure that the strap information is
read as expected and passed to FSP.

Change-Id: I69583f35ffc219bae9ce06bd4ba9898ed0d4d21d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39812
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian
2020-04-17 10:16:52 -06:00
committed by Patrick Georgi
parent 816c5cb9fc
commit da38715ec3
3 changed files with 11 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/dedede/romstage.c
View File

@@ -6,8 +6,10 @@
*/ */
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <gpio.h>
#include <soc/meminit.h> #include <soc/meminit.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *memupd) void mainboard_memory_init_params(FSPM_UPD *memupd)
{ {
@@ -16,7 +18,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
.read_type = READ_SPD_CBFS, .read_type = READ_SPD_CBFS,
.spd_spec.spd_index = variant_memory_sku(), .spd_spec.spd_index = variant_memory_sku(),
}; };
/* TODO: Read the resistor strap to get number of memory segments. */ bool half_populated = !gpio_get(GPIO_MEM_CH_SEL);
bool half_populated = 0;
memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
} }

5
src/mainboard/google/dedede/variants/baseboard/gpio.c
View File

@@ -348,7 +348,7 @@ static const struct pad_config gpio_table[] = {
/* S0 : RAM_STRAP_4 */ /* S0 : RAM_STRAP_4 */
PAD_NC(GPP_S0, NONE), PAD_CFG_GPI(GPP_S0, UP_5K, DEEP),
/* S1 : RSVD_STRAP */ /* S1 : RSVD_STRAP */
PAD_NC(GPP_S1, NONE), PAD_NC(GPP_S1, NONE),
/* S2 : DMIC1_CLK */ /* S2 : DMIC1_CLK */
@@ -416,6 +416,9 @@ static const struct pad_config early_gpio_table[] = {
/* H19 : BT_DISABLE_L */ /* H19 : BT_DISABLE_L */
PAD_CFG_GPO(GPP_H19, 0, DEEP), PAD_CFG_GPO(GPP_H19, 0, DEEP),
/* S0 : RAM_STRAP_4 */
PAD_CFG_GPI(GPP_S0, UP_5K, DEEP),
}; };
const struct pad_config *__weak variant_gpio_table(size_t *num) const struct pad_config *__weak variant_gpio_table(size_t *num)

3
src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
View File

@@ -26,4 +26,7 @@
#define GPIO_MEM_CONFIG_2 GPP_C4 #define GPIO_MEM_CONFIG_2 GPP_C4
#define GPIO_MEM_CONFIG_3 GPP_C5 #define GPIO_MEM_CONFIG_3 GPP_C5
/* Memory channel select strap - 0: half-populated, 1: fully-populated */
#define GPIO_MEM_CH_SEL GPP_S0
#endif /* __BASEBOARD_GPIO_H__ */ #endif /* __BASEBOARD_GPIO_H__ */