soc/intel/skylake: Set PsysPmax value

According to doc #543977 Power Architecture Guide, PsysPmax is the
maximum platform power. It maps to the full-scale of Psys signal.
This patch adds a "psys_pmax" member in chip information which allows
boards to set up maximum platform power.

BUG=b:71594855
BRANCH=None
TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz
     chromeos-mrc coreboot chromeos-bootimage" & ensure correct
     PsysPmax value is passed to FSP-S through UPD. Verfied on
     KBL-R and KBL-U SKUs.

Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/skylake/chip.h

@@ -110,6 +110,9 @@ struct soc_intel_skylake_config {
 	/* PL4 Value in Watts */
 	u32 tdp_pl4;
 
+	/* Estimated maximum platform power in Watts */
+	u16 psys_pmax;
+
 	/*
 	 * The following fields come from FspUpdVpd.h.
 	 * These are configuration values that are passed to FSP during