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inteltool/ahci: Add Skylake support

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The SATA device moved from 0:1f.2 to 0:17.0, 0:1f.2 became PMC. We
detect that by checking the PCI device class.

The ABAR MMIO space has grown to 2KiB and up to 8 ports are supported
now. For backwards compatibility, only dump port registers of ports
that are enabled in the Ports Implemented (PI) register.

Change-Id: I8e0f07d7359d92f689882b5afefa5ffb3766ee8b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber
2017-03-30 17:47:24 +02:00
committed by Stefan Reinauer
parent 0660c6c1ff
commit da94e171b5
3 changed files with 43 additions and 17 deletions
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43
util/inteltool/ahci.c
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@@ -2,6 +2,7 @@
* ahci.c: dump AHCI registers
*
* Copyright (C) 2016 Iru Cai
* Copyright (C) 2017 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,9 +20,6 @@
#include <inttypes.h>
#include "inteltool.h"
#define NUM_SATA_PORTS 6
#define MMIO_SIZE 0x400
static const char *ghc_regs[] = {
"CAP", "GHC", "IS", "PI",
"VS", "CCC_CTL", "CCC_PORTS", "EM_LOC",
@@ -41,17 +39,24 @@ static const char *port_ctl_regs[] = {
int print_ahci(struct pci_dev *ahci)
{
uint64_t mmio_phys;
size_t mmio_size;
uint8_t *mmio;
uint32_t i, j;
if (!ahci) {
puts("No SATA device found");
return 0;
}
printf("\n============= AHCI Registers ==============\n\n");
mmio_phys = ahci->base_addr[5] & ~0x7ULL;
if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA)
mmio_size = 0x800;
else
mmio_size = 0x400;
const pciaddr_t mmio_phys = ahci->base_addr[5] & ~0x7ULL;
printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)mmio_phys);
mmio = map_physical(mmio_phys, MMIO_SIZE);
mmio = map_physical(mmio_phys, mmio_size);
if (mmio == NULL) {
perror("Error mapping MMIO");
exit(1);
@@ -63,15 +68,27 @@ int print_ahci(struct pci_dev *ahci)
(i / 4 < NUM_GHC) ? ghc_regs[i / 4]:"Reserved");
}
for (i = 0; i < NUM_SATA_PORTS; i++) {
printf("\nPort %d Control Registers:\n", i);
uint8_t *mmio_port = mmio + 0x100 + i * 0x80;
for (j = 0; j < 0x80; j += 4) {
printf("0x%03x: 0x%08x (%s)\n", 0x100+i*0x80+j, *(uint32_t *)(mmio_port + j),
(j / 4 < NUM_PORTCTL) ? port_ctl_regs[j / 4]:"Reserved");
const size_t max_ports = (mmio_size - 0x100) / 0x80;
for (i = 0; i < max_ports; i++) {
if (*(uint32_t *)(mmio + 0x0c) & 1 << i) {
printf("\nPort %d Control Registers:\n", i);
uint8_t *mmio_port = mmio + 0x100 + i * 0x80;
for (j = 0; j < 0x80; j += 4) {
printf("0x%03x: 0x%08x (%s)\n", 0x100+i*0x80+j,
*(uint32_t *)(mmio_port + j),
(j / 4 < NUM_PORTCTL) ?
port_ctl_regs[j / 4] :
"Reserved");
}
}
}
unmap_physical((void *)mmio, MMIO_SIZE);
if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA) {
puts("\nOther registers:");
for (i = 0x500; i < mmio_size; i += 4)
printf("0x%03x: 0x%08x\n", i, *(uint32_t *)(mmio + i));
}
unmap_physical((void *)mmio, mmio_size);
return 0;
}