From dafe9d6fe0510aa35f21c9afae31b426b270ca93 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Thu, 19 Nov 2020 15:49:37 -0700
Subject: [PATCH] Add CPU LTR

Change-Id: I91c494b2d085abc6bea10bda0bc13fb31eec2cff
---
 src/mainboard/system76/galp5/ramstage.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/system76/galp5/ramstage.c b/src/mainboard/system76/galp5/ramstage.c
index 1f212147a8..a580240404 100644
--- a/src/mainboard/system76/galp5/ramstage.c
+++ b/src/mainboard/system76/galp5/ramstage.c
@@ -6,6 +6,7 @@
 void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
 	// CPU RP Config
 	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
 	params->CpuPcieRpPtmEnabled[0] = 0;
 
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));