sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/starlabs/starbook: Disable ASPM in coreboot

Browse Source 
ASPM is already configured by FSP so disable it in coreboot to
reduce boot time by a whopping 34ms.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
This commit is contained in:
Sean Rhodes
2023-03-27 10:59:02 +01:00
committed by Felix Held
parent 7d6ae2b72c
commit db8ef01e30
1 changed files with 21 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
src/mainboard/starlabs/starbook/Kconfig
View File

@@ -145,9 +145,30 @@ config EDK2_BOOTSPLASH_FILE
string string
default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
config PCIEXP_ASPM
bool
default n
help
FSP is already taking care of ASPM, which is configured through the devicetree in coreboot
on Alderlake Platforms. Disable it to save some boot time.
config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
default 32 default 32
config PCIEXP_L1_SUB_STATE
bool
default n
help
Enabling PCIe L1 sub states is already done in FSP.
Disable it to save some boot time.
config PCIEXP_CLK_PM
bool
default n
help
Enabling PCIe clock power management is already done in FSP.
Disable it to save some boot time
config SOC_INTEL_CSE_SEND_EOP_EARLY config SOC_INTEL_CSE_SEND_EOP_EARLY
default n if BOARD_STARLABS_STARBOOK_ADL default n if BOARD_STARLABS_STARBOOK_ADL