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inteltool: add initial support for Nehalem

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Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)

Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.

The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...

Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Tauner
2013-06-20 18:05:06 +02:00
committed by Ronald G. Minnich
parent a390d77966
commit dbc6fcd021
4 changed files with 54 additions and 2 deletions
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1
util/inteltool/inteltool.h
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@@ -151,6 +151,7 @@
#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
/* Intel starts counting these generations with the integration of the DRAM controller */
#define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */
#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */
#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */