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inteltool: add initial support for Nehalem

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Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)

Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.

The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...

Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Tauner
2013-06-20 18:05:06 +02:00
committed by Ronald G. Minnich
parent a390d77966
commit dbc6fcd021
4 changed files with 54 additions and 2 deletions
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2
util/inteltool/memory.c
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@@ -246,7 +246,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
mch_registers = NULL; /* No public documentation */
mch_registers = NULL; /* TODO: 322812 */
break;
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
mch_registers = sandybridge_mch_registers;