cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF

Change-Id: I7e8866d76d7f286e10160d7dc4f21f01a913bfee
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6286
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>

src/cpu/amd/agesa/family10/Makefile.inc

@@ -301,4 +301,3 @@ subdirs-y += ../../../x86/cache
 subdirs-y += ../../../x86/mtrr
 subdirs-y += ../../../x86/pae
 subdirs-y += ../../../x86/smm
-

src/cpu/amd/agesa/family15/Makefile.inc

@@ -27,4 +27,3 @@ subdirs-y += ../../../x86/smm
 
 ramstage-y += chip_name.c
 ramstage-y += model_15_init.c
-

src/cpu/amd/geode_gx2/Makefile.inc

@@ -12,4 +12,3 @@ cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
 vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
 vsa-type = stage
 vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)
-

src/cpu/amd/geode_lx/Makefile.inc

@@ -12,4 +12,3 @@ cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
 vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
 vsa-type = stage
 vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)
-

src/cpu/intel/slot_1/Makefile.inc

@@ -33,4 +33,3 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
-

src/cpu/intel/slot_2/Makefile.inc

@@ -26,4 +26,3 @@ subdirs-y += ../../x86/lapic
 subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
-

src/cpu/intel/socket_441/Makefile.inc

@@ -8,4 +8,3 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
-

src/cpu/intel/socket_PGA370/Makefile.inc

@@ -28,4 +28,3 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
 cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
-

src/cpu/intel/socket_mPGA478/Makefile.inc

@@ -8,4 +8,3 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
-

src/cpu/intel/socket_mPGA603/Makefile.inc

@@ -9,4 +9,3 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
-

src/cpu/intel/socket_mPGA604/Makefile.inc

@@ -11,4 +11,3 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 
 cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-

src/cpu/x86/name/Makefile.inc

@@ -18,4 +18,3 @@
 ##
 
 ramstage-y += name.c
-

src/cpu/x86/tsc/Makefile.inc

@@ -3,4 +3,3 @@ romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
 ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
 smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
 endif
-