nb/intel/sandybridge: Make the mainboard_early_init hook optional

This adds an empty weakly linked default. The rationale behind this
change is that without the callback some features might not work
but that the result is likely still able to boot, so it can be made
optional.

Change-Id: I62c8010aa81fc45d208e9293feb2f45b45f34a82
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/asus/h61m-cs/romstage.c

@@ -52,10 +52,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	nuvoton_pnp_enter_conf_state(SIO_DEV);

src/mainboard/asus/maximus_iv_gene-z/romstage.c

@@ -48,10 +48,6 @@ void mainboard_rcba_config(void)
 {
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);

src/mainboard/asus/p8h61-m_lx/romstage.c

@@ -51,10 +51,6 @@ void mainboard_rcba_config(void)
 {
 }
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

src/mainboard/asus/p8h61-m_pro/romstage.c

@@ -53,10 +53,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	/* Enable UART */

src/mainboard/asus/p8z77-m_pro/romstage.c

@@ -56,10 +56,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 0, 2, 6 }  /* Port 13: Unused. Asus propietary DEBUG_PORT ??? */
 };
 
-void mainboard_early_init(int s3resume)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	/* Setup COM/UART */