soc/intel/xeon_sp/spr: Use official microcodes

Use the official microcode updates from intel-microcode submodule
by default. Downstream users can still decide to use their own files.

Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81637
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>

src/soc/intel/xeon_sp/spr/Kconfig

@@ -3,7 +3,6 @@
 config SOC_INTEL_SAPPHIRERAPIDS_SP
 	bool
 	select FSP_NVS_DATA_POST_SILICON_INIT
-	select MICROCODE_BLOB_NOT_HOOKED_UP
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select DISABLE_ACPI_HIBERNATE
 	select DEFAULT_X2APIC_RUNTIME

src/soc/intel/xeon_sp/spr/Makefile.mk

@@ -19,4 +19,7 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr
 
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8f-08
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-cf-02
+
 endif ## CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP