baytrail: first pass at lpss device initialization

This commit does the common parts for all LPSS devices
that are enabled: enable snoop in IOSF and enable power
management. Additionally, the i2c devices are taken out of
reset.

BUG=chrome-os-partner:23790
BRANCH=None
TEST=Built and booted with modified kernel-next. I2C bus devices
     show up and I see 0x10 on one of the buses.

Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176424
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4969
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/soc/intel/baytrail/Makefile.inc

@@ -41,6 +41,7 @@ ramstage-y += acpi.c
 ramstage-y += lpe.c
 ramstage-y += scc.c
 ramstage-y += emmc.c
+ramstage-y += lpss.c
 
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c