pcengines/apu2: add board support
Initial work based on db-ft3b-ls and code released by Eltan. Board boots with some limitation. Now the AGESA binary is harcoded and board specific until it's fixed by the SoC vendor. memtest86+ from external repo skips looking for SPD on SMBus, which when performed cause memtest86+ to hang. Still didn't tried whole test suit. SeaBIOS 1.9.3 have some problems with USB which lead to no booting in some cases. Full log: https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872 SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios) works fine. Those changes are planned for upstream. Information about obtaining and booting Voyage Linux: https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/14138 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Piotr Król
committed by
Kyösti Mälkki
Kyösti Mälkki
parent
cff3b095c2
commit
dcd2f17ff4
166
src/mainboard/pcengines/apu2/mptable.c
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166
src/mainboard/pcengines/apu2/mptable.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdfam15.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#if 0
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u8 picr_data[FCH_INT_TABLE_SIZE] = {
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0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
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0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* 10 - 17 */
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0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
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0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F, /* 30 - 37 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
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0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
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// 0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00, /* 50 - 57 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
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0x00,0x00,0x1F /* 60 - 62 */
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};
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u8 intr_data[FCH_INT_TABLE_SIZE] = {
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0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F, /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
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0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* 08 - 0F */
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0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10, /* 10 - 17 */
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0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 18 - 1F */
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0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, /* 20 - 27 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 28 - 2F */
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0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00, /* 30 - 37 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 38 - 3F */
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0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00, /* 40 - 47 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 48 - 4F */
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// 0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00, /* 50 - 57 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 50 - 57 */
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 58 - 5F */
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0x00,0x00,0x1F /* 60 - 62 */
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};
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#endif
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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/* Intialize the MP_Table */
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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/*
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* Type 0: Processor Entries:
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* LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
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* CPU Signature (Stepping, Model, Family),
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* Feature Flags
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*/
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smp_write_processors(mc);
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/*
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* Type 1: Bus Entries:
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* Bus ID, Bus Type
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*/
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mptable_write_buses(mc, NULL, &bus_isa);
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/*
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* Type 2: I/O APICs:
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* APIC ID, Version, APIC Flags:EN, Address
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*/
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u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
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u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
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smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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/*
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* Type 3: I/O Interrupt Table Entries:
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* Int Type, Int Polarity, Int Level, Source Bus ID,
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* Source Bus IRQ, Dest APIC ID, Dest PIN#
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*/
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mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, int_sign, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
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/* SMBUS / ACPI */
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PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
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/* SD card */
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PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
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/* USB */
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PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
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PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
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PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
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PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
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PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
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PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
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PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
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/* SATA */
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PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
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/* on board NIC & Slot PCIE */
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PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
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PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
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/* GPP0 */
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PCI_INT(0x0, 0x2, 0x0, 0x10); // Network 3
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/* GPP1 */
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PCI_INT(0x0, 0x2, 0x1, 0x11); // Network 2
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/* GPP2 */
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PCI_INT(0x0, 0x2, 0x2, 0x12); // Network 1
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/* GPP3 */
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PCI_INT(0x0, 0x2, 0x3, 0x13); // mPCI
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/* GPP4 */
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PCI_INT(0x0, 0x2, 0x4, 0x14); // mPCI
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IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */
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return (unsigned long)smp_write_config_table(v);
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}
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