pcengines/apu2: add board support

Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.

Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.

memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.

SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872

SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.

Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder

Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/14138
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/southbridge/amd/pi/hudson/early_setup.c

@@ -25,12 +25,12 @@
 #include <cbmem.h>
 #include "hudson.h"
 #include "pci_devs.h"
+#include <Fch/Fch.h>
 
 #if IS_ENABLED(CONFIG_HUDSON_UART)
 
 #include <cpu/x86/msr.h>
 #include <delay.h>
-#include <Fch/Fch.h>
 
 void configure_hudson_uart(void)
 {
@@ -174,4 +174,20 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 	return nvram_pos;
 }
 
+void hudson_clk_output_48Mhz(void)
+{
+	u32 data, *memptr;
+
+	/*
+	 * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
+	 * 48Mhz will be on ball AP13 (FT3b package)
+	 */
+	memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 );
+	data = *memptr;
+
+	/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
+	data &= (u32)~(1<<2);
+	*memptr = data;
+}
+
 #endif