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skl mainboards/dt: Move genx_dec settings into LPC device scope

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Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2024-06-23 03:39:24 +02:00
parent 6c83a71b0a
commit dcddc53fde
24 changed files with 104 additions and 106 deletions
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6
src/mainboard/51nb/x210/devicetree.cb
View File

@ -26,9 +26,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
# Disable DPTF
register "dptf_enable" = "0"
@ -114,6 +111,9 @@ chip soc/intel/skylake
device ref pcie_rp4 on end
device ref pcie_rp9 on end
device ref lpc_espi on
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
chip ec/51nb/npce985la0dx
device pnp 0c09.0 on end
device pnp 4e.5 on end

10
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -18,11 +18,6 @@ chip soc/intel/skylake
register "lpc_iod" = "0x0070"
register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66"
# CPLD host command ranges are in 0x280-0x2BF
# EC PNP registers are at 0x6e and 0x6f
register "gen1_dec" = "0x003c0281"
register "gen3_dec" = "0x0004006d"
# LPC serial IRQ
register "serirq_mode" = "SERIRQ_CONTINUOUS"
@ -221,6 +216,11 @@ chip soc/intel/skylake
device ref uart0 on end
device ref emmc on end
device ref lpc_espi on
# CPLD host command ranges are in 0x280-0x2BF
# EC PNP registers are at 0x6e and 0x6f
register "gen1_dec" = "0x003c0281"
register "gen3_dec" = "0x0004006d"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end

12
src/mainboard/google/eve/devicetree.cb
View File

@ -29,12 +29,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# FSP Configuration
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
@ -379,6 +373,12 @@ chip soc/intel/skylake
end
device ref emmc on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

12
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -52,12 +52,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
@ -407,6 +401,12 @@ chip soc/intel/skylake
end
device ref sdxc on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

8
src/mainboard/google/glados/devicetree.cb
View File

@ -27,10 +27,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# Enable DPTF
register "dptf_enable" = "1"
@ -97,6 +93,10 @@ chip soc/intel/skylake
device ref uart0 on end
device ref emmc on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end

12
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -27,12 +27,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_B"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
@ -363,6 +357,12 @@ chip soc/intel/skylake
device ref sdio off end
device ref sdxc off end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

12
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -18,12 +18,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
@ -372,6 +366,12 @@ chip soc/intel/skylake
device ref sdio off end
device ref sdxc on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

12
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -27,12 +27,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
@ -463,6 +457,12 @@ chip soc/intel/skylake
device ref sdio off end
device ref sdxc off end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

12
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -27,12 +27,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
@ -410,6 +404,12 @@ chip soc/intel/skylake
device ref sdio off end
device ref sdxc on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

12
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -20,12 +20,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
@ -401,6 +395,12 @@ chip soc/intel/skylake
device ref sdio off end
device ref sdxc off end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

12
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -27,12 +27,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
@ -376,6 +370,12 @@ chip soc/intel/skylake
device ref sdio off end
device ref sdxc on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

12
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -27,12 +27,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# Enable DPTF
register "dptf_enable" = "1"
@ -355,6 +349,12 @@ chip soc/intel/skylake
device ref sdio off end
device ref sdxc on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec
device pnp 0c09.0 on end
end

7
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
View File

@ -13,9 +13,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
# Enable DPTF
register "dptf_enable" = "1"
@ -127,6 +124,10 @@ chip soc/intel/skylake
device ref emmc on end
device ref sdxc on end
device ref smbus on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
end
device ref fast_spi on end
end
end

6
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View File

@ -3,9 +3,6 @@ chip soc/intel/skylake
# GPE configuration
register "gpe0_dw0" = "GPP_C"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen2_dec" = "0x000c0201"
# FSP Configuration
register "DspEnable" = "1"
@ -123,6 +120,9 @@ chip soc/intel/skylake
device ref pcie_rp9 on end # x1 WLAN
device ref pcie_rp10 on end # x1 WIGIG
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen2_dec" = "0x000c0201"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end

6
src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
View File

@ -10,9 +10,6 @@ chip soc/intel/skylake
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen2_dec" = "0x000c0201"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
@ -164,6 +161,9 @@ chip soc/intel/skylake
device ref pcie_rp5 on end
device ref pcie_rp6 on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen2_dec" = "0x000c0201"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end

8
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -13,10 +13,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# Enable DPTF
register "dptf_enable" = "1"
@ -235,6 +231,10 @@ chip soc/intel/skylake
device ref emmc on end
device ref sdxc on end
device ref lpc_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end

7
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -25,10 +25,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f
register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef
register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff
# Disable DPTF
register "dptf_enable" = "0"
@ -173,6 +169,9 @@ chip soc/intel/skylake
device ref pcie_rp11 on end
device ref pcie_rp12 on end
device ref lpc_espi on
register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f
register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef
register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end

9
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -12,11 +12,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
register "gen1_dec" = "0x00fc0201"
register "gen2_dec" = "0x007c0a01"
register "gen3_dec" = "0x000c03e1"
register "gen4_dec" = "0x001c02e1"
register "eist_enable" = "1"
# Disable DPTF
@ -202,6 +197,10 @@ chip soc/intel/skylake
"SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
end
device ref lpc_espi on
register "gen1_dec" = "0x00fc0201"
register "gen2_dec" = "0x007c0a01"
register "gen3_dec" = "0x000c03e1"
register "gen4_dec" = "0x001c02e1"
chip superio/ite/it8772f
register "TMPIN1.mode" = "THERMAL_RESISTOR"
register "TMPIN2.mode" = "THERMAL_RESISTOR"

5
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -34,9 +34,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00000381"
# Disable DPTF
register "dptf_enable" = "0"
@ -153,6 +150,8 @@ chip soc/intel/skylake
device ref pcie_rp5 on end
device ref pcie_rp9 on end
device ref lpc_espi on
# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00000381"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end

6
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -15,9 +15,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
# Disable DPTF
register "dptf_enable" = "0"
@ -175,6 +172,9 @@ chip soc/intel/skylake
device ref pcie_rp5 on end
device ref pcie_rp9 on end
device ref lpc_espi on
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
chip superio/ite/it8528e
device pnp 6e.1 off end
device pnp 6e.2 off end

6
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
View File

@ -8,9 +8,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
# Additional FSP Configuration
# This board has an IGD with no output.
register "PrimaryDisplay" = "Display_Auto"
@ -83,6 +80,9 @@ chip soc/intel/skylake
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device ref lpc_espi on
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
chip drivers/ipmi
# On cold boot it takes a while for the BMC to start the IPMI service
register "wait_for_bmc" = "1"

6
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
View File

@ -8,9 +8,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
# FIXME: find out why FSP crashes without this
register "PchHdaVcType" = "Vc1"
@ -67,6 +64,9 @@ chip soc/intel/skylake
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
end
device ref lpc_espi on
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
chip drivers/ipmi
use pch_gpio as gpio_dev
register "post_complete_gpio" = "GPP_B20"

6
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
View File

@ -8,9 +8,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
device domain 0 on
subsystemid 0x15d9 0x0896 inherit
device ref south_xhci on
@ -84,6 +81,9 @@ chip soc/intel/skylake
end
end
device ref lpc_espi on
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
chip drivers/ipmi
use pch_gpio as gpio_dev
register "bmc_jumper_gpio" = "GPP_D22" # JPB1

6
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
View File

@ -8,9 +8,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
# Additional FSP Configuration
# This board has an IGD with no output.
register "PrimaryDisplay" = "Display_Auto"
@ -71,6 +68,9 @@ chip soc/intel/skylake
end
end
device ref lpc_espi on
register "gen1_dec" = "0x007c0a01" # Super IO SWC
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
chip drivers/ipmi
# On cold boot it takes a while for the BMC to start the IPMI service
register "wait_for_bmc" = "1"