sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge: remove STONEYRIDGE_ACPI_IO_BASE Kconfig option

Browse Source 
No board in tree selects a different base address, so this can be
removed from Kconfig and be treated like the other base addresses in the
I/O space that are defines in iomap.h.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iec3d4476e3a6a5d2b226edef4c41f503a0c81f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held
2021-02-05 01:06:59 +01:00
parent 2f8228d3c9
commit dd1fb4e38c
2 changed files with 1 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/amd/stoneyridge/Kconfig
View File

@@ -250,13 +250,6 @@ config SERIRQ_CONTINUOUS_MODE
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
config STONEYRIDGE_ACPI_IO_BASE
hex
default 0x400
help
Base address for the ACPI registers.
This value must match the hardcoded value of AGESA.
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL
hex

2
src/soc/amd/stoneyridge/include/soc/iomap.h
View File

@@ -27,7 +27,7 @@
/* I/O Ranges */
#define ACPI_SMI_CTL_PORT 0xb2
#define ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE
#define ACPI_IO_BASE 0x400
#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) /* 2 bytes */
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */