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cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support

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Prepare a common cache as ram for CPU's featuring a Non eviction mode
MSR.

Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26789
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2018-06-03 12:04:26 +02:00
parent 3a4edb6ea8
commit dd4d895136
5 changed files with 265 additions and 0 deletions
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6
src/cpu/intel/model_206ax/Makefile.inc
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@@ -17,5 +17,11 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
else
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
postcar-y += ../car/non-evict/exit_car.S
endif
romstage-y += ../car/romstage.c