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intel/gma: Only enable bus mastering if we are going to use it

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Also fix wrong 32-bit writes.

Change-Id: Ib038f0cd558223536da08ba2264774db11cd8357
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40727
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2020-04-26 19:46:35 +02:00
parent dfdf102000
commit dd59762729
9 changed files with 23 additions and 55 deletions
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8
src/northbridge/intel/gm45/gma.c
View File

@ -144,7 +144,6 @@ static void gma_pm_init_post_vbios(struct device *const dev,
static void gma_func0_init(struct device *dev)
{
u32 reg32;
u8 *mmio;
u8 edid_data_lvds[128];
struct edid edid_lvds;
@ -152,16 +151,13 @@ static void gma_func0_init(struct device *dev)
intel_gma_init_igd_opregion();
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (gtt_res == NULL)
return;
mmio = res2mmio(gtt_res, 0, 0);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
/* PCI Init, will run VBIOS */

9
src/northbridge/intel/haswell/gma.c
View File

@ -458,21 +458,18 @@ static void gma_enable_swsci(void)
static void gma_func0_init(struct device *dev)
{
int lightup_ok = 0;
u32 reg32;
intel_gma_init_igd_opregion();
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
gma_pm_init_pre_vbios(dev);
/* Pre panel init */
gma_setup_panel(dev);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {

13
src/northbridge/intel/i945/gma.c
View File

@ -660,8 +660,6 @@ static void gma_ngi(struct device *const dev)
static void gma_func0_init(struct device *dev)
{
u32 reg32;
intel_gma_init_igd_opregion();
/* Unconditionally reset graphics */
@ -672,9 +670,8 @@ static void gma_func0_init(struct device *dev)
while (pci_read_config8(dev, GDRST) & 1)
;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
@ -713,12 +710,10 @@ static void gma_func0_disable(struct device *dev)
static void gma_func1_init(struct device *dev)
{
u32 reg32;
u8 val;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
if (get_option(&val, "tft_brightness") == CB_SUCCESS)
pci_write_config8(dev, 0xf4, val);

8
src/northbridge/intel/ironlake/gma.c
View File

@ -135,14 +135,10 @@ static void gma_enable_swsci(void)
static void gma_func0_init(struct device *dev)
{
u32 reg32;
intel_gma_init_igd_opregion();
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!gtt_res || !gtt_res->base)

8
src/northbridge/intel/pineview/gma.c
View File

@ -218,14 +218,10 @@ static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
static void gma_func0_init(struct device *dev)
{
u32 reg32;
intel_gma_init_igd_opregion();
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
/* PCI init, will run VBIOS */

10
src/northbridge/intel/sandybridge/gma.c
View File

@ -585,18 +585,14 @@ static void gma_enable_swsci(void)
static void gma_func0_init(struct device *dev)
{
u32 reg32;
intel_gma_init_igd_opregion();
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Init graphics power management */
gma_pm_init_pre_vbios(dev);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
if (!CONFIG(MAINBOARD_USE_LIBGFXINIT))
/* PCI Init, will run VBIOS */
pci_dev_init(dev);

8
src/northbridge/intel/x4x/gma.c
View File

@ -22,14 +22,10 @@
static void gma_func0_init(struct device *dev)
{
u32 reg32;
intel_gma_init_igd_opregion();
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* configure GMBUSFREQ */
pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc);

8
src/soc/intel/broadwell/igd.c
View File

@ -496,15 +496,13 @@ static void igd_init(struct device *dev)
intel_gma_init_igd_opregion();
/* IGD needs to be Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!gtt_res || !gtt_res->base)
return;
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
#if CONFIG(CHROMEOS)

6
src/soc/intel/common/block/graphics/graphics.c
View File

@ -45,10 +45,8 @@ static void gma_init(struct device *const dev)
if (CONFIG(RUN_FSP_GOP))
return;
/* IGD needs to Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
if (!acpi_is_wakeup_s3() && display_init_required()) {