soc/intel/icelake: Make use of gpio_pm_configure()

Provide option in chip.h to set dynamic local clock gating
setting.

BUG=b:130764684
TEST=Able to build and boot ICL.

Change-Id: Ic30a490aadb8cc9c05a19a05533ab0196c69b7f1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/icelake/chip.c

@@ -103,6 +103,27 @@ const char *soc_acpi_name(const struct device *dev)
 }
 #endif
 
+/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
+static void soc_fill_gpio_pm_configuration(void)
+{
+	uint8_t value[TOTAL_GPIO_COMM];
+	const struct device *dev;
+	dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0);
+	if (!dev || !dev->chip_info)
+		return;
+
+	const config_t *config = dev->chip_info;
+
+	if (config->gpio_override_pm)
+		memcpy(value, config->gpio_pm, sizeof(uint8_t) *
+			TOTAL_GPIO_COMM);
+	else
+		memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+			TOTAL_GPIO_COMM);
+
+	gpio_pm_configure(value, TOTAL_GPIO_COMM);
+}
+
 void soc_init_pre_device(void *chip_info)
 {
 	/* Snapshot the current GPIO IRQ polarities. FSP is setting a
@@ -117,6 +138,8 @@ void soc_init_pre_device(void *chip_info)
 
 	/* Restore GPIO IRQ polarities back to previous settings. */
 	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
+	soc_fill_gpio_pm_configuration();
 }
 
 static void pci_domain_set_resources(struct device *dev)

src/soc/intel/icelake/chip.h

@@ -18,6 +18,7 @@
 
 #include <intelblocks/chip.h>
 #include <drivers/i2c/designware/dw_i2c.h>
+#include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
 #include <stdint.h>
 #include <soc/gpe.h>
@@ -263,6 +264,25 @@ struct soc_intel_icelake_config {
 		FORCE_ENABLE,
 		FORCE_DISABLE,
 	} CnviBtAudioOffload;
+
+	/*
+	 * Override GPIO PM configuration:
+	 * 0: Use FSP default GPIO PM program,
+	 * 1: coreboot to override GPIO PM program
+	 */
+	uint8_t gpio_override_pm;
+
+	/*
+	 * GPIO PM configuration: 0 to disable, 1 to enable power gating
+	 * Bit 6-7: Reserved
+	 * Bit 5: MISCCFG_GPSIDEDPCGEN
+	 * Bit 4: MISCCFG_GPRCOMPCDLCGEN
+	 * Bit 3: MISCCFG_GPRTCDLCGEN
+	 * Bit 2: MISCCFG_GSXLCGEN
+	 * Bit 1: MISCCFG_GPDPCGEN
+	 * Bit 0: MISCCFG_GPDLCGEN
+	 */
+	uint8_t gpio_pm[TOTAL_GPIO_COMM];
 };
 
 typedef struct soc_intel_icelake_config config_t;

src/soc/intel/icelake/gpio.c

@@ -76,8 +76,9 @@ static const struct pad_group icl_community5_groups[] = {
 	INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320),		/* GPP_S */
 };
 
-static const struct pad_community icl_communities[] = {
+static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = {
-	{ /* GPP G, B, A */
+	/* GPP G, B, A */
+	[COMM_0] = {
 		.port = PID_GPIOCOM0,
 		.first_pad = GPP_G0,
 		.last_pad = GPP_A23,
@@ -95,7 +96,9 @@ static const struct pad_community icl_communities[] = {
 		.num_reset_vals = ARRAY_SIZE(rst_map_com0),
 		.groups = icl_community0_groups,
 		.num_groups = ARRAY_SIZE(icl_community0_groups),
-	}, { /* GPP H, D, F */
+	},
+	/* GPP H, D, F */
+	[COMM_1] = {
 		.port = PID_GPIOCOM1,
 		.first_pad = GPP_H0,
 		.last_pad = GPP_F19,
@@ -113,7 +116,9 @@ static const struct pad_community icl_communities[] = {
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = icl_community1_groups,
 		.num_groups = ARRAY_SIZE(icl_community1_groups),
-	}, { /* GPD */
+	},
+	 /* GPD */
+	[COMM_2] = {
 		.port = PID_GPIOCOM2,
 		.first_pad = GPD0,
 		.last_pad = GPD11,
@@ -131,7 +136,9 @@ static const struct pad_community icl_communities[] = {
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = icl_community2_groups,
 		.num_groups = ARRAY_SIZE(icl_community2_groups),
-	}, { /* GPP C, E */
+	},
+	/* GPP C, E */
+	[COMM_3] = {
 		.port = PID_GPIOCOM4,
 		.first_pad = GPP_C0,
 		.last_pad = GPP_E23,
@@ -149,7 +156,9 @@ static const struct pad_community icl_communities[] = {
 		.num_reset_vals = ARRAY_SIZE(rst_map),
 		.groups = icl_community4_groups,
 		.num_groups = ARRAY_SIZE(icl_community4_groups),
-	}, { /* GPP R, S */
+	},
+	/* GPP R, S */
+	[COMM_4] = {
 		.port = PID_GPIOCOM5,
 		.first_pad = GPP_R0,
 		.last_pad = GPP_S7,

src/soc/intel/icelake/include/soc/gpio_soc_defs.h

@@ -281,4 +281,12 @@
 #define NUM_GPIO_COM5_PADS	(GPP_S7 - GPP_R0 + 1)
 
 #define TOTAL_PADS	205
+
+#define COMM_0		0
+#define COMM_1		1
+#define COMM_2		2
+#define COMM_3		3
+#define COMM_4		4
+#define TOTAL_GPIO_COMM	5
+
 #endif