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nb/intel/x4x: Reflow long lines

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Try to unbreak long lines and user-visible strings.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: I1bbf08cf665157840380517302ca581718e3cbe4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-03-26 23:21:02 +01:00
committed by Nico Huber
parent 5c3160ed80
commit dd7ce4e1d3
6 changed files with 133 additions and 254 deletions
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72
src/northbridge/intel/x4x/dq_dqs.c
View File

@ -8,8 +8,7 @@
#include "raminit.h" #include "raminit.h"
#include "x4x.h" #include "x4x.h"
static void print_dll_setting(const struct dll_setting *dll_setting, static void print_dll_setting(const struct dll_setting *dll_setting, u8 default_verbose)
u8 default_verbose)
{ {
u8 debug_level = default_verbose ? BIOS_DEBUG : RAM_DEBUG; u8 debug_level = default_verbose ? BIOS_DEBUG : RAM_DEBUG;
@ -75,11 +74,9 @@ static void set_db(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
static const u8 max_tap[3] = {12, 10, 13}; static const u8 max_tap[3] = {12, 10, 13};
static int increment_dq_dqs(const struct sysinfo *s, static int increment_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
struct dll_setting *dq_dqs_setting)
{ {
u8 max_tap_val = max_tap[s->selected_timings.mem_clk u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
- MEM_CLOCK_800MHz];
if (dq_dqs_setting->pi < 6) { if (dq_dqs_setting->pi < 6) {
dq_dqs_setting->pi += 1; dq_dqs_setting->pi += 1;
@ -102,11 +99,9 @@ static int increment_dq_dqs(const struct sysinfo *s,
return CB_SUCCESS; return CB_SUCCESS;
} }
static int decrement_dq_dqs(const struct sysinfo *s, static int decrement_dq_dqs(const struct sysinfo *s, struct dll_setting *dq_dqs_setting)
struct dll_setting *dq_dqs_setting)
{ {
u8 max_tap_val = max_tap[s->selected_timings.mem_clk u8 max_tap_val = max_tap[s->selected_timings.mem_clk - MEM_CLOCK_800MHz];
- MEM_CLOCK_800MHz];
if (dq_dqs_setting->pi > 0) { if (dq_dqs_setting->pi > 0) {
dq_dqs_setting->pi -= 1; dq_dqs_setting->pi -= 1;
@ -159,8 +154,7 @@ enum training_modes {
FAILING = 1 FAILING = 1
}; };
static u8 test_dq_aligned(const struct sysinfo *s, static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel)
const u8 channel)
{ {
u32 address; u32 address;
int rank, lane; int rank, lane;
@ -174,17 +168,14 @@ static u8 test_dq_aligned(const struct sysinfo *s,
for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) { for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) {
if ((count1 % 16) == 0) if ((count1 % 16) == 0)
MCHBAR32(0xf90) = 1; MCHBAR32(0xf90) = 1;
const u32 pattern = const u32 pattern = write_training_schedule[count1];
write_training_schedule[count1];
write32((u32 *)address + 8 * count1, pattern); write32((u32 *)address + 8 * count1, pattern);
write32((u32 *)address + 8 * count1 + 4, write32((u32 *)address + 8 * count1 + 4, pattern);
pattern);
} }
const u32 good = write_training_schedule[count]; const u32 good = write_training_schedule[count];
write32(&data[0], read32((u32 *)address + 8 * count)); write32(&data[0], read32((u32 *)address + 8 * count));
write32(&data[4], write32(&data[4], read32((u32 *)address + 8 * count + 4));
read32((u32 *)address + 8 * count + 4));
FOR_EACH_BYTELANE(lane) { FOR_EACH_BYTELANE(lane) {
u8 expected = (good >> ((lane % 4) * 8)) & 0xff; u8 expected = (good >> ((lane % 4) * 8)) & 0xff;
if (data[lane] != expected) if (data[lane] != expected)
@ -235,8 +226,8 @@ static int find_dq_limit(const struct sysinfo *s, const u8 channel,
success_mask &= ~(1 << lane); success_mask &= ~(1 << lane);
} }
if (status == CB_ERR) { if (status == CB_ERR) {
printk(BIOS_CRIT, "Could not find a case of %s " printk(BIOS_CRIT,
"writes on CH%d, lane %d\n", "Could not find a case of %s writes on CH%d, lane %d\n",
expected_result == FAILING ? "failing" expected_result == FAILING ? "failing"
: "succeeding", channel, lane); : "succeeding", channel, lane);
return CB_ERR; return CB_ERR;
@ -281,19 +272,15 @@ int do_write_training(struct sysinfo *s)
/* Start from DQS settings */ /* Start from DQS settings */
memcpy(dq_setting, s->dqs_settings[channel], sizeof(dq_setting)); memcpy(dq_setting, s->dqs_settings[channel], sizeof(dq_setting));
if (find_dq_limit(s, channel, dq_setting, dq_lower, if (find_dq_limit(s, channel, dq_setting, dq_lower, SUCCEEDING)) {
SUCCEEDING)) { printk(BIOS_CRIT, "Could not find working lower limit DQ setting\n");
printk(BIOS_CRIT,
"Could not find working lower limit DQ setting\n");
return CB_ERR; return CB_ERR;
} }
memcpy(dq_upper, dq_lower, sizeof(dq_lower)); memcpy(dq_upper, dq_lower, sizeof(dq_lower));
if (find_dq_limit(s, channel, dq_setting, dq_upper, if (find_dq_limit(s, channel, dq_setting, dq_upper, FAILING)) {
FAILING)) { printk(BIOS_WARNING, "Could not find failing upper limit DQ setting\n");
printk(BIOS_WARNING,
"Could not find failing upper limit DQ setting\n");
return CB_ERR; return CB_ERR;
} }
@ -302,8 +289,8 @@ int do_write_training(struct sysinfo *s)
dq_upper[lane] -= CONSISTENCY - 1; dq_upper[lane] -= CONSISTENCY - 1;
u8 dq_center = (dq_upper[lane] + dq_lower[lane]) / 2; u8 dq_center = (dq_upper[lane] + dq_lower[lane]) / 2;
printk(RAM_DEBUG, "Centered value for DQ DLL:" printk(RAM_DEBUG,
" ch%d, lane %d, #steps = %d\n", "Centered value for DQ DLL: ch%d, lane %d, #steps = %d\n",
channel, lane, dq_center); channel, lane, dq_center);
for (i = 0; i < dq_center; i++) { for (i = 0; i < dq_center; i++) {
/* Should never happen */ /* Should never happen */
@ -403,13 +390,10 @@ static int rt_find_dqs_limit(struct sysinfo *s, u8 channel,
} }
if (expected_result == SUCCEEDING) { if (expected_result == SUCCEEDING) {
printk(BIOS_CRIT, printk(BIOS_CRIT, "Could not find RT DQS setting\n");
"Could not find RT DQS setting\n");
return CB_ERR; return CB_ERR;
} else { } else {
printk(RAM_DEBUG, printk(RAM_DEBUG, "Read succeeded over all DQS settings, continuing\n");
"Read succeeded over all DQS"
" settings, continuing\n");
return CB_SUCCESS; return CB_SUCCESS;
} }
} }
@ -664,8 +648,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank)
if (bytelane_ok & (1 << lane)) if (bytelane_ok & (1 << lane))
continue; continue;
printk(RAM_SPEW, "%d, %d, %02d, %d," printk(RAM_SPEW, "%d, %d, %02d, %d, lane%d sample: %d\n",
" lane%d sample: %d\n",
dqs_setting[lane].coarse, dqs_setting[lane].coarse,
dqs_setting[lane].clk_delay, dqs_setting[lane].clk_delay,
dqs_setting[lane].tap, dqs_setting[lane].tap,
@ -785,8 +768,7 @@ void search_write_leveling(struct sysinfo *s)
printk(BIOS_DEBUG, "\tCH%d\n", ch); printk(BIOS_DEBUG, "\tCH%d\n", ch);
config = chanconfig_lut[s->dimm_config[ch]]; config = chanconfig_lut[s->dimm_config[ch]];
MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e;
MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e;
MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) & MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) &
~0x3fff) | 0x3fff; ~0x3fff) | 0x3fff;
MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) =
@ -803,12 +785,9 @@ void search_write_leveling(struct sysinfo *s)
MCHBAR8(0x298 + 2 + 0x400 * ch) = MCHBAR8(0x298 + 2 + 0x400 * ch) =
(MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f) (MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f)
| odt_force[config][rank0]; | odt_force[config][rank0];
MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) | 0x4e;
& ~0x7e) | 0x4e; MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
MCHBAR8(0x5d9 + 0x400 * ch) = MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00014000;
(MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff)
| 0x00014000;
if (increment_to_dqs_edge(s, ch, rank0)) if (increment_to_dqs_edge(s, ch, rank0))
die("Write Leveling failed!"); die("Write Leveling failed!");
@ -827,8 +806,7 @@ void search_write_leveling(struct sysinfo *s)
set_rank_write_level(s, ch, config, rank0, rank0, 0); set_rank_write_level(s, ch, config, rank0, rank0, 0);
send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12); send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12);
MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e;
& ~0x0e) | 0x0e;
MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch)
& ~0x3fff) | 0x1807; & ~0x3fff) | 0x1807;
MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f; MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;

5
src/northbridge/intel/x4x/memmap.c
View File

@ -18,8 +18,7 @@
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ /** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms) u32 decode_igd_memory_size(const u32 gms)
{ {
static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, static const u16 ggc2uma[] = {0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352};
32, 48, 64, 128, 256, 96, 160, 224, 352 };
if (gms >= ARRAY_SIZE(ggc2uma)) if (gms >= ARRAY_SIZE(ggc2uma))
die("Bad Graphics Mode Select (GMS) setting.\n"); die("Bad Graphics Mode Select (GMS) setting.\n");
@ -30,7 +29,7 @@ u32 decode_igd_memory_size(const u32 gms)
/** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ /** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */
u32 decode_igd_gtt_size(const u32 gsm) u32 decode_igd_gtt_size(const u32 gsm)
{ {
static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; static const u8 ggc2gtt[] = {0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
if (gsm >= ARRAY_SIZE(ggc2gtt)) if (gsm >= ARRAY_SIZE(ggc2gtt))
die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); die("Bad GTT Graphics Memory Size (GGMS) setting.\n");

10
src/northbridge/intel/x4x/northbridge.c
View File

@ -41,8 +41,7 @@ static void mch_domain_read_resources(struct device *dev)
tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff; tom = pci_read_config16(mch, D0F0_TOM) & 0x01ff;
tom <<= 26; tom <<= 26;
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom);
touud, tolud, tom);
tomk = tolud >> 10; tomk = tolud >> 10;
@ -77,8 +76,7 @@ static void mch_domain_read_resources(struct device *dev)
tomk -= delta_cbmem; tomk -= delta_cbmem;
uma_sizek += delta_cbmem; uma_sizek += delta_cbmem;
printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%xK\n", delta_cbmem);
delta_cbmem);
printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
@ -101,8 +99,8 @@ static void mch_domain_read_resources(struct device *dev)
(touud - top32memk) >> 10); (touud - top32memk) >> 10);
} }
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n",
"size=0x%08x\n", tomk << 10, uma_sizek << 10); tomk << 10, uma_sizek << 10);
uma_resource(dev, index++, tomk, uma_sizek); uma_resource(dev, index++, tomk, uma_sizek);
/* Reserve high memory where the NB BARs are up to 4GiB */ /* Reserve high memory where the NB BARs are up to 4GiB */

155
src/northbridge/intel/x4x/raminit.c
View File

@ -34,8 +34,7 @@ static u16 ddr3_get_crc(u8 device, u8 len)
return spd_ddr3_calc_unique_crc(raw_spd, len); return spd_ddr3_calc_unique_crc(raw_spd, len);
} }
static enum cb_err verify_spds(const u8 *spd_map, static enum cb_err verify_spds(const u8 *spd_map, const struct sysinfo *ctrl_cached)
const struct sysinfo *ctrl_cached)
{ {
int i; int i;
u16 crc; u16 crc;
@ -44,11 +43,9 @@ static enum cb_err verify_spds(const u8 *spd_map,
if (!(spd_map[i])) if (!(spd_map[i]))
continue; continue;
int len = smbus_read_byte(spd_map[i], 0); int len = smbus_read_byte(spd_map[i], 0);
if (len < 0 && ctrl_cached->dimms[i].card_type if (len < 0 && ctrl_cached->dimms[i].card_type == RAW_CARD_UNPOPULATED)
== RAW_CARD_UNPOPULATED)
continue; continue;
if (len > 0 && ctrl_cached->dimms[i].card_type if (len > 0 && ctrl_cached->dimms[i].card_type == RAW_CARD_UNPOPULATED)
== RAW_CARD_UNPOPULATED)
return CB_ERR; return CB_ERR;
if (ctrl_cached->spd_type == DDR2) if (ctrl_cached->spd_type == DDR2)
@ -79,8 +76,7 @@ struct abs_timings {
#define CTRL_MIN_TCLK_DDR2 TCK_400MHZ #define CTRL_MIN_TCLK_DDR2 TCK_400MHZ
static void select_cas_dramfreq_ddr2(struct sysinfo *s, static void select_cas_dramfreq_ddr2(struct sysinfo *s, const struct abs_timings *saved_timings)
const struct abs_timings *saved_timings)
{ {
u8 try_cas; u8 try_cas;
/* Currently only these CAS are supported */ /* Currently only these CAS are supported */
@ -152,8 +148,7 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
if (!(decoded_dimm.width & (0x08 | 0x10))) { if (!(decoded_dimm.width & (0x08 | 0x10))) {
printk(BIOS_ERR, printk(BIOS_ERR, "DIMM%d Unsupported width: x%d. Disabling dimm\n",
"DIMM%d Unsupported width: x%d. Disabling dimm\n",
dimm_idx, s->dimms[dimm_idx].width); dimm_idx, s->dimms[dimm_idx].width);
return CB_ERR; return CB_ERR;
} }
@ -166,8 +161,7 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
* size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory'
* The formula is pagesize in KiB = width * 2^col_bits / 8. * The formula is pagesize in KiB = width * 2^col_bits / 8.
*/ */
s->dimms[dimm_idx].page_size = decoded_dimm.width * s->dimms[dimm_idx].page_size = decoded_dimm.width * (1 << decoded_dimm.col_bits) / 8;
(1 << decoded_dimm.col_bits) / 8;
switch (decoded_dimm.banks) { switch (decoded_dimm.banks) {
case 4: case 4:
@ -177,8 +171,7 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
s->dimms[dimm_idx].n_banks = N_BANKS_8; s->dimms[dimm_idx].n_banks = N_BANKS_8;
break; break;
default: default:
printk(BIOS_ERR, printk(BIOS_ERR, "DIMM%d Unsupported #banks: x%d. Disabling dimm\n",
"DIMM%d Unsupported #banks: x%d. Disabling dimm\n",
dimm_idx, decoded_dimm.banks); dimm_idx, decoded_dimm.banks);
return CB_ERR; return CB_ERR;
} }
@ -189,22 +182,14 @@ static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
saved_timings->cas_supported &= decoded_dimm.cas_supported; saved_timings->cas_supported &= decoded_dimm.cas_supported;
saved_timings->min_tRAS = saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); saved_timings->min_tRP = MAX(saved_timings->min_tRP, decoded_dimm.tRP);
saved_timings->min_tRP = saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
MAX(saved_timings->min_tRP, decoded_dimm.tRP); saved_timings->min_tWR = MAX(saved_timings->min_tWR, decoded_dimm.tWR);
saved_timings->min_tRCD = saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); saved_timings->min_tWTR = MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
saved_timings->min_tWR = saved_timings->min_tRRD = MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
MAX(saved_timings->min_tWR, decoded_dimm.tWR); saved_timings->min_tRTP = MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
saved_timings->min_tRFC =
MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
saved_timings->min_tWTR =
MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
saved_timings->min_tRRD =
MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
saved_timings->min_tRTP =
MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
if (!(saved_timings->cas_supported & (1 << i))) if (!(saved_timings->cas_supported & (1 << i)))
saved_timings->min_tCLK_cas[i] = 0; saved_timings->min_tCLK_cas[i] = 0;
@ -231,8 +216,7 @@ static void normalize_tCLK(u32 *tCLK)
*tCLK = 0; *tCLK = 0;
} }
static void select_cas_dramfreq_ddr3(struct sysinfo *s, static void select_cas_dramfreq_ddr3(struct sysinfo *s, struct abs_timings *saved_timings)
struct abs_timings *saved_timings)
{ {
/* /*
* various constraints must be fulfilled: * various constraints must be fulfilled:
@ -278,9 +262,9 @@ static void select_cas_dramfreq_ddr3(struct sysinfo *s,
min_tCLK = MAX(min_tCLK, saved_timings->min_tclk); min_tCLK = MAX(min_tCLK, saved_timings->min_tclk);
if (min_tCLK == 0) { if (min_tCLK == 0) {
printk(BIOS_ERR, "DRAM frequency is under lowest supported " printk(BIOS_ERR,
"frequency (400 MHz). Increasing to 400 MHz " "DRAM frequency is under lowest supported frequency (400 MHz). "
"as last resort"); "Increasing to 400 MHz as last resort");
min_tCLK = TCK_400MHZ; min_tCLK = TCK_400MHZ;
} }
@ -337,8 +321,7 @@ static void workaround_stacked_mode(struct sysinfo *s)
if (s->spd_type == DDR2) if (s->spd_type == DDR2)
return; return;
/* Does not matter if only one channel is populated */ /* Does not matter if only one channel is populated */
if (!CHANNEL_IS_POPULATED(s->dimms, 0) if (!CHANNEL_IS_POPULATED(s->dimms, 0) || !CHANNEL_IS_POPULATED(s->dimms, 1))
|| !CHANNEL_IS_POPULATED(s->dimms, 1))
return; return;
if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz) if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz)
return; return;
@ -373,8 +356,7 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
* for all densities except the 256Mb device, which has a 1KB page size." * for all densities except the 256Mb device, which has a 1KB page size."
* Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' * Micron, 'TN-47-16 Designing for High-Density DDR2 Memory'
*/ */
s->dimms[dimm_idx].page_size = decoded_dimm.width * s->dimms[dimm_idx].page_size = decoded_dimm.width * (1 << decoded_dimm.col_bits) / 8;
(1 << decoded_dimm.col_bits) / 8;
s->dimms[dimm_idx].n_banks = N_BANKS_8; /* Always 8 banks on ddr3?? */ s->dimms[dimm_idx].n_banks = N_BANKS_8; /* Always 8 banks on ddr3?? */
@ -382,61 +364,40 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
s->dimms[dimm_idx].rows = decoded_dimm.row_bits; s->dimms[dimm_idx].rows = decoded_dimm.row_bits;
s->dimms[dimm_idx].cols = decoded_dimm.col_bits; s->dimms[dimm_idx].cols = decoded_dimm.col_bits;
saved_timings->min_tRAS = saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS);
MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); saved_timings->min_tRP = MAX(saved_timings->min_tRP, decoded_dimm.tRP);
saved_timings->min_tRP = saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, decoded_dimm.tRCD);
MAX(saved_timings->min_tRP, decoded_dimm.tRP); saved_timings->min_tWR = MAX(saved_timings->min_tWR, decoded_dimm.tWR);
saved_timings->min_tRCD = saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); saved_timings->min_tWTR = MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
saved_timings->min_tWR = saved_timings->min_tRRD = MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
MAX(saved_timings->min_tWR, decoded_dimm.tWR); saved_timings->min_tRTP = MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
saved_timings->min_tRFC = saved_timings->min_tAA = MAX(saved_timings->min_tAA, decoded_dimm.tAA);
MAX(saved_timings->min_tRFC, decoded_dimm.tRFC);
saved_timings->min_tWTR =
MAX(saved_timings->min_tWTR, decoded_dimm.tWTR);
saved_timings->min_tRRD =
MAX(saved_timings->min_tRRD, decoded_dimm.tRRD);
saved_timings->min_tRTP =
MAX(saved_timings->min_tRTP, decoded_dimm.tRTP);
saved_timings->min_tAA =
MAX(saved_timings->min_tAA, decoded_dimm.tAA);
saved_timings->cas_supported &= decoded_dimm.cas_supported; saved_timings->cas_supported &= decoded_dimm.cas_supported;
s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd, s->dimms[dimm_idx].spd_crc = spd_ddr3_calc_unique_crc(raw_spd, raw_spd[0]);
raw_spd[0]);
s->dimms[dimm_idx].mirrored = decoded_dimm.flags.pins_mirrored; s->dimms[dimm_idx].mirrored = decoded_dimm.flags.pins_mirrored;
return CB_SUCCESS; return CB_SUCCESS;
} }
static void select_discrete_timings(struct sysinfo *s, static void select_discrete_timings(struct sysinfo *s, const struct abs_timings *timings)
const struct abs_timings *timings)
{ {
s->selected_timings.tRAS = DIV_ROUND_UP(timings->min_tRAS, s->selected_timings.tRAS = DIV_ROUND_UP(timings->min_tRAS, s->selected_timings.tclk);
s->selected_timings.tclk); s->selected_timings.tRP = DIV_ROUND_UP(timings->min_tRP, s->selected_timings.tclk);
s->selected_timings.tRP = DIV_ROUND_UP(timings->min_tRP, s->selected_timings.tRCD = DIV_ROUND_UP(timings->min_tRCD, s->selected_timings.tclk);
s->selected_timings.tclk); s->selected_timings.tWR = DIV_ROUND_UP(timings->min_tWR, s->selected_timings.tclk);
s->selected_timings.tRCD = DIV_ROUND_UP(timings->min_tRCD, s->selected_timings.tRFC = DIV_ROUND_UP(timings->min_tRFC, s->selected_timings.tclk);
s->selected_timings.tclk); s->selected_timings.tWTR = DIV_ROUND_UP(timings->min_tWTR, s->selected_timings.tclk);
s->selected_timings.tWR = DIV_ROUND_UP(timings->min_tWR, s->selected_timings.tRRD = DIV_ROUND_UP(timings->min_tRRD, s->selected_timings.tclk);
s->selected_timings.tclk); s->selected_timings.tRTP = DIV_ROUND_UP(timings->min_tRTP, s->selected_timings.tclk);
s->selected_timings.tRFC = DIV_ROUND_UP(timings->min_tRFC,
s->selected_timings.tclk);
s->selected_timings.tWTR = DIV_ROUND_UP(timings->min_tWTR,
s->selected_timings.tclk);
s->selected_timings.tRRD = DIV_ROUND_UP(timings->min_tRRD,
s->selected_timings.tclk);
s->selected_timings.tRTP = DIV_ROUND_UP(timings->min_tRTP,
s->selected_timings.tclk);
} }
static void print_selected_timings(struct sysinfo *s) static void print_selected_timings(struct sysinfo *s)
{ {
printk(BIOS_DEBUG, "Selected timings:\n"); printk(BIOS_DEBUG, "Selected timings:\n");
printk(BIOS_DEBUG, "\tFSB: %dMHz\n", printk(BIOS_DEBUG, "\tFSB: %dMHz\n", fsb_to_mhz(s->selected_timings.fsb_clk));
fsb_to_mhz(s->selected_timings.fsb_clk)); printk(BIOS_DEBUG, "\tDDR: %dMHz\n", ddr_to_mhz(s->selected_timings.mem_clk));
printk(BIOS_DEBUG, "\tDDR: %dMHz\n",
ddr_to_mhz(s->selected_timings.mem_clk));
printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS); printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS);
printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS); printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS);
@ -505,8 +466,8 @@ static void decode_spd_select_timings(struct sysinfo *s)
printk(BIOS_DEBUG, "Decoding dimm %d\n", i); printk(BIOS_DEBUG, "Decoding dimm %d\n", i);
if (i2c_eeprom_read(device, 0, 128, raw_spd) != 128) { if (i2c_eeprom_read(device, 0, 128, raw_spd) != 128) {
printk(BIOS_DEBUG, "i2c block operation failed," printk(BIOS_DEBUG,
" trying smbus byte operation.\n"); "i2c block operation failed, trying smbus byte operation.\n");
for (j = 0; j < 128; j++) for (j = 0; j < 128; j++)
raw_spd[j] = smbus_read_byte(device, j); raw_spd[j] = smbus_read_byte(device, j);
} }
@ -514,16 +475,14 @@ static void decode_spd_select_timings(struct sysinfo *s)
if (s->spd_type == DDR2){ if (s->spd_type == DDR2){
if (ddr2_save_dimminfo(i, raw_spd, &saved_timings, s)) { if (ddr2_save_dimminfo(i, raw_spd, &saved_timings, s)) {
printk(BIOS_WARNING, printk(BIOS_WARNING,
"Encountered problems with SPD, " "Encountered problems with SPD, skipping this DIMM.\n");
"skipping this DIMM.\n");
s->dimms[i].card_type = RAW_CARD_UNPOPULATED; s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
continue; continue;
} }
} else { /* DDR3 */ } else { /* DDR3 */
if (ddr3_save_dimminfo(i, raw_spd, &saved_timings, s)) { if (ddr3_save_dimminfo(i, raw_spd, &saved_timings, s)) {
printk(BIOS_WARNING, printk(BIOS_WARNING,
"Encountered problems with SPD, " "Encountered problems with SPD, skipping this DIMM.\n");
"skipping this DIMM.\n");
/* something in decoded SPD was unsupported */ /* something in decoded SPD was unsupported */
s->dimms[i].card_type = RAW_CARD_UNPOPULATED; s->dimms[i].card_type = RAW_CARD_UNPOPULATED;
continue; continue;
@ -560,11 +519,9 @@ static void find_dimm_config(struct sysinfo *s)
else else
die("Dual-rank x16 not supported\n"); die("Dual-rank x16 not supported\n");
} }
s->dimm_config[chan] |= s->dimm_config[chan] |= dimm_config << (i % DIMMS_PER_CHANNEL) * 2;
dimm_config << (i % DIMMS_PER_CHANNEL) * 2;
} }
printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, printk(BIOS_DEBUG, " Config[CH%d] : %d\n", chan, s->dimm_config[chan]);
s->dimm_config[chan]);
} }
} }
@ -577,11 +534,9 @@ static void checkreset_ddr2(int boot_path)
if (boot_path >= 1) { if (boot_path >= 1) {
pmsts = MCHBAR32(PMSTS_MCHBAR); pmsts = MCHBAR32(PMSTS_MCHBAR);
if (!(pmsts & 1)) if (!(pmsts & 1))
printk(BIOS_DEBUG, printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n");
"Channel 0 possibly not in self refresh\n");
if (!(pmsts & 2)) if (!(pmsts & 2))
printk(BIOS_DEBUG, printk(BIOS_DEBUG, "Channel 1 possibly not in self refresh\n");
"Channel 1 possibly not in self refresh\n");
} }
pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
@ -638,8 +593,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
/* check SPD checksum to make sure the DIMMs haven't been replaced */ /* check SPD checksum to make sure the DIMMs haven't been replaced */
fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS; fast_boot = verify_spds(spd_map, ctrl_cached) == CB_SUCCESS;
if (!fast_boot) { if (!fast_boot) {
printk(BIOS_DEBUG, "SPD checksums don't match," printk(BIOS_DEBUG,
" dimm's have been replaced\n"); "SPD checksums don't match, dimm's have been replaced\n");
} else { } else {
find_fsb_speed(&s); find_fsb_speed(&s);
fast_boot = s.max_fsb == ctrl_cached->max_fsb; fast_boot = s.max_fsb == ctrl_cached->max_fsb;
@ -667,8 +622,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
/* Detect dimms per channel */ /* Detect dimms per channel */
reg8 = pci_read_config8(HOST_BRIDGE, 0xe9); reg8 = pci_read_config8(HOST_BRIDGE, 0xe9);
printk(BIOS_DEBUG, "Dimms per channel: %d\n", printk(BIOS_DEBUG, "Dimms per channel: %d\n", (reg8 & 0x10) ? 1 : 2);
(reg8 & 0x10) ? 1 : 2);
mchinfo_ddr2(&s); mchinfo_ddr2(&s);
@ -692,8 +646,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
cbmem_was_inited = !cbmem_recovery(s3resume); cbmem_was_inited = !cbmem_recovery(s3resume);
if (!fast_boot) if (!fast_boot)
mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &s, sizeof(s));
&s, sizeof(s));
if (s3resume && !cbmem_was_inited) { if (s3resume && !cbmem_was_inited) {
/* Failed S3 resume, reset to come up cleanly */ /* Failed S3 resume, reset to come up cleanly */

105
src/northbridge/intel/x4x/raminit_ddr23.c
View File

@ -367,8 +367,7 @@ void dqset(u8 ch, u8 lane, const struct dll_setting *setting)
} }
} }
void rt_set_dqs(u8 channel, u8 lane, u8 rank, void rt_set_dqs(u8 channel, u8 lane, u8 rank, struct rt_dqs_setting *dqs_setting)
struct rt_dqs_setting *dqs_setting)
{ {
u16 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4); u16 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4);
u16 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4); u16 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4);
@ -525,12 +524,10 @@ static void program_timings(struct sysinfo *s)
reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1; reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1;
if (s->spd_type == DDR2) if (s->spd_type == DDR2)
reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk reg32 |= ddr2_x252_tab[s->selected_timings.mem_clk
- MEM_CLOCK_667MHz][reg8][pagemod] - MEM_CLOCK_667MHz][reg8][pagemod] << 22;
<< 22;
else else
reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk reg32 |= ddr3_x252_tab[s->selected_timings.mem_clk
- MEM_CLOCK_800MHz][reg8][pagemod] - MEM_CLOCK_800MHz][reg8][pagemod] << 22;
<< 22;
} }
MCHBAR32(0x400*i + 0x252) = reg32; MCHBAR32(0x400*i + 0x252) = reg32;
@ -675,8 +672,7 @@ static void program_dll(struct sysinfo *s)
u16 reg16 = 0; u16 reg16 = 0;
u32 reg32 = 0; u32 reg32 = 0;
const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, 0x08, 0x10 };
0x08, 0x10 };
MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04); MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04);
MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8); MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8);
@ -718,8 +714,7 @@ static void program_dll(struct sysinfo *s)
udelay(1); /* 533ns */ udelay(1); /* 533ns */
/* ME related */ /* ME related */
MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, s->spd_type == DDR2 ? 0x551803 : 0x555801);
s->spd_type == DDR2 ? 0x551803 : 0x555801);
MCHBAR16_AND(0x1b4, ~0x800); MCHBAR16_AND(0x1b4, ~0x800);
if (s->spd_type == DDR2) { if (s->spd_type == DDR2) {
@ -750,34 +745,25 @@ static void program_dll(struct sysinfo *s)
if (s->spd_type == DDR2) { if (s->spd_type == DDR2) {
if (!CHANNEL_IS_POPULATED(s->dimms, i)) { if (!CHANNEL_IS_POPULATED(s->dimms, i)) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG, "No dimms in channel %d\n", i);
"No dimms in channel %d\n", i);
reg8 = 0x3f; reg8 = 0x3f;
} else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i);
"DimmA populated only in channel %d\n",
i);
reg8 = 0x38; reg8 = 0x38;
} else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i);
"DimmB populated only in channel %d\n",
i);
reg8 = 0x7; reg8 = 0x7;
} else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i);
"Both dimms populated in channel %d\n",
i);
reg8 = 0; reg8 = 0;
} else { } else {
die("Unhandled case\n"); die("Unhandled case\n");
} }
MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, (u32)(reg8 << 24));
(u32)(reg8 << 24));
} else { /* DDR3 */ } else { /* DDR3 */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) { FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {
MCHBAR8_AND(0x400 * i + 0x5a0 + 3, MCHBAR8_AND(0x400 * i + 0x5a0 + 3, ~rank2clken[r + i * 4]);
~rank2clken[r + i * 4]);
} }
} }
} /* END EACH CHANNEL */ } /* END EACH CHANNEL */
@ -798,10 +784,8 @@ static void program_dll(struct sysinfo *s)
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc); MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc);
MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc); MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc);
MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, s->spd_type == DDR2 ? 0x70 : 0x60);
s->spd_type == DDR2 ? 0x70 : 0x60); MCHBAR16_AND_OR(0x400*i + 0x590, 0, s->spd_type == DDR2 ? 0x5555 : 0xa955);
MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff,
s->spd_type == DDR2 ? 0x5555 : 0xa955);
} }
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
@ -1025,8 +1009,7 @@ static void set_all_dq_dqs_dll_settings(struct sysinfo *s)
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
FOR_EACH_BYTELANE(lane) { FOR_EACH_BYTELANE(lane) {
FOR_EACH_RANK_IN_CHANNEL(rank) { FOR_EACH_RANK_IN_CHANNEL(rank) {
rt_set_dqs(ch, lane, rank, rt_set_dqs(ch, lane, rank, &s->rt_dqs[ch][lane]);
&s->rt_dqs[ch][lane]);
} }
dqsset(ch, lane, &s->dqs_settings[ch][lane]); dqsset(ch, lane, &s->dqs_settings[ch][lane]);
dqset(ch, lane, &s->dq_settings[ch][lane]); dqset(ch, lane, &s->dq_settings[ch][lane]);
@ -1117,8 +1100,7 @@ static void prog_rcomp(struct sysinfo *s)
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, ~0x3f3f3f3f, x39e[j]); MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, ~0x3f3f3f3f, x39e[j]);
/* Override command group strength multiplier */ /* Override command group strength multiplier */
if (s->spd_type == DDR3 && if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
MCHBAR16_AND_OR(0x378 + 0x400 * i, ~0xffff, 0xcccc); MCHBAR16_AND_OR(0x378 + 0x400 * i, ~0xffff, 0xcccc);
} }
MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]); MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]);
@ -1186,15 +1168,11 @@ static void program_odt(struct sysinfo *s)
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
if (s->spd_type == DDR2) { if (s->spd_type == DDR2) {
MCHBAR16(0x400 * i + 0x298) = MCHBAR16(0x400 * i + 0x298) = ddr2_odt[s->dimm_config[i]][1];
ddr2_odt[s->dimm_config[i]][1]; MCHBAR16(0x400 * i + 0x294) = ddr2_odt[s->dimm_config[i]][0];
MCHBAR16(0x400 * i + 0x294) =
ddr2_odt[s->dimm_config[i]][0];
} else { } else {
MCHBAR16(0x400 * i + 0x298) = MCHBAR16(0x400 * i + 0x298) = ddr3_odt[s->dimm_config[i]][1];
ddr3_odt[s->dimm_config[i]][1]; MCHBAR16(0x400 * i + 0x294) = ddr3_odt[s->dimm_config[i]][0];
MCHBAR16(0x400 * i + 0x294) =
ddr3_odt[s->dimm_config[i]][0];
} }
u16 reg16 = MCHBAR16(0x400*i + 0x29c); u16 reg16 = MCHBAR16(0x400*i + 0x29c);
reg16 &= ~0xfff; reg16 &= ~0xfff;
@ -1445,11 +1423,9 @@ static void sdram_recover_receive_enable(const struct sysinfo *s)
MCHBAR32(0x400 * channel + 0x248) = reg32; MCHBAR32(0x400 * channel + 0x248) = reg32;
FOR_EACH_BYTELANE(lane) { FOR_EACH_BYTELANE(lane) {
medium |= s->rcven_t[channel].medium[lane] medium |= s->rcven_t[channel].medium[lane] << (lane * 2);
<< (lane * 2);
coarse_offset |= coarse_offset |=
(s->rcven_t[channel].coarse_offset[lane] & 0x3) (s->rcven_t[channel].coarse_offset[lane] & 0x3) << (lane * 2);
<< (lane * 2);
pi_tap = MCHBAR8(0x400 * channel + 0x560 + lane * 4); pi_tap = MCHBAR8(0x400 * channel + 0x560 + lane * 4);
pi_tap &= ~0x7f; pi_tap &= ~0x7f;
@ -1546,11 +1522,9 @@ static void set_dradrb(struct sysinfo *s)
} }
} }
if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0))
ONLY_DIMMB_IS_POPULATED(s->dimms, 0))
MCHBAR8_OR(0x260, 1); MCHBAR8_OR(0x260, 1);
if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1))
ONLY_DIMMB_IS_POPULATED(s->dimms, 1))
MCHBAR8_OR(0x660, 1); MCHBAR8_OR(0x660, 1);
/* DRB */ /* DRB */
@ -1659,17 +1633,14 @@ static void set_dradrb(struct sysinfo *s)
single_channel_offset = 0; single_channel_offset = 0;
} else if (size_me == 0) { } else if (size_me == 0) {
if (size_ch0 > size_ch1) if (size_ch0 > size_ch1)
single_channel_offset = dual_channel_size / 2 single_channel_offset = dual_channel_size / 2 + single_channel_size;
+ single_channel_size;
else else
single_channel_offset = dual_channel_size / 2; single_channel_offset = dual_channel_size / 2;
} else { } else {
if ((size_ch0 > size_ch1) && ((map & 0x7) == 4)) if ((size_ch0 > size_ch1) && ((map & 0x7) == 4))
single_channel_offset = dual_channel_size / 2 single_channel_offset = dual_channel_size / 2 + single_channel_size;
+ single_channel_size;
else else
single_channel_offset = dual_channel_size / 2 single_channel_offset = dual_channel_size / 2 + size_me;
+ size_me;
} }
MCHBAR16(0x108) = single_channel_offset; MCHBAR16(0x108) = single_channel_offset;
@ -1683,8 +1654,7 @@ static void configure_mmap(struct sysinfo *s)
u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit;
u32 mmiostart, umasizem; u32 mmiostart, umasizem;
u16 ggc; u16 ggc;
u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 };
160, 224, 352 };
u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
ggc = pci_read_config16(HOST_BRIDGE, 0x52); ggc = pci_read_config16(HOST_BRIDGE, 0x52);
@ -1721,10 +1691,8 @@ static void configure_mmap(struct sysinfo *s)
pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4); pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4);
pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6); pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6);
if (reclaim) { if (reclaim) {
pci_write_config16(HOST_BRIDGE, 0x98, pci_write_config16(HOST_BRIDGE, 0x98, (u16)(reclaimbase >> 6));
(u16)(reclaimbase >> 6)); pci_write_config16(HOST_BRIDGE, 0x9a, (u16)(reclaimlimit >> 6));
pci_write_config16(HOST_BRIDGE, 0x9a,
(u16)(reclaimlimit >> 6));
} }
pci_write_config16(HOST_BRIDGE, 0xa2, touud); pci_write_config16(HOST_BRIDGE, 0xa2, touud);
pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20); pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20);
@ -2091,18 +2059,15 @@ void do_raminit(struct sysinfo *s, int fast_boot)
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
reg32 = (2 << 18); reg32 = (2 << 18);
reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
[s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0] [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][0] << 13;
<< 13;
if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz &&
s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz && s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz &&
ch == 1) { ch == 1) {
reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk] reg32 |= (post_jedec_tab[s->selected_timings.fsb_clk]
[s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] - 1) << 8;
- 1) << 8;
} else { } else {
reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
[s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] << 8;
<< 8;
} }
MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32); MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32);
MCHBAR8_AND(0x400*ch + 0x274, ~0x80); MCHBAR8_AND(0x400*ch + 0x274, ~0x80);
@ -2186,11 +2151,9 @@ void do_raminit(struct sysinfo *s, int fast_boot)
* and is only needed in case of ME being used. * and is only needed in case of ME being used.
*/ */
if (ME_UMA_SIZEMB != 0) { if (ME_UMA_SIZEMB != 0) {
if (RANK_IS_POPULATED(s->dimms, 0, 0) if (RANK_IS_POPULATED(s->dimms, 0, 0) || RANK_IS_POPULATED(s->dimms, 1, 0))
|| RANK_IS_POPULATED(s->dimms, 1, 0))
MCHBAR8_OR(0xa2f, 1 << 0); MCHBAR8_OR(0xa2f, 1 << 0);
if (RANK_IS_POPULATED(s->dimms, 0, 1) if (RANK_IS_POPULATED(s->dimms, 0, 1) || RANK_IS_POPULATED(s->dimms, 1, 1))
|| RANK_IS_POPULATED(s->dimms, 1, 1))
MCHBAR8_OR(0xa2f, 1 << 1); MCHBAR8_OR(0xa2f, 1 << 1);
MCHBAR32_OR(0xa30, 1 << 26); MCHBAR32_OR(0xa30, 1 << 26);
} }

40
src/northbridge/intel/x4x/rcven.c
View File

@ -42,15 +42,13 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel)
return (MCHBAR8(sample_offset) >> 6) & 1; return (MCHBAR8(sample_offset) >> 6) & 1;
} }
static void program_timing(const struct rec_timing *timing, u8 channel, static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane)
u8 lane)
{ {
u32 reg32; u32 reg32;
u16 reg16; u16 reg16;
u8 reg8; u8 reg8;
printk(RAM_SPEW, " Programming timings:" printk(RAM_SPEW, " Programming timings:Coarse: %d, Medium: %d, TAP: %d, PI: %d\n",
"Coarse: %d, Medium: %d, TAP: %d, PI: %d\n",
timing->coarse, timing->medium, timing->tap, timing->pi); timing->coarse, timing->medium, timing->tap, timing->pi);
reg32 = MCHBAR32(0x400 * channel + 0x248); reg32 = MCHBAR32(0x400 * channel + 0x248);
@ -122,15 +120,12 @@ static int decrease_tap(struct rec_timing *timing)
return 0; return 0;
} }
static int decr_coarse_low(u8 channel, u8 lane, u32 addr, static int decr_coarse_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
struct rec_timing *timing)
{ {
printk(RAM_DEBUG, printk(RAM_DEBUG, " Decreasing coarse until high to low transition is found\n");
" Decreasing coarse until high to low transition is found\n");
while (sampledqs(addr, lane, channel) != DQS_LOW) { while (sampledqs(addr, lane, channel) != DQS_LOW) {
if (timing->coarse == 0) { if (timing->coarse == 0) {
printk(BIOS_CRIT, printk(BIOS_CRIT, "Couldn't find DQS-high 0 indicator, halt\n");
"Couldn't find DQS-high 0 indicator, halt\n");
return -1; return -1;
} }
timing->coarse--; timing->coarse--;
@ -141,11 +136,9 @@ static int decr_coarse_low(u8 channel, u8 lane, u32 addr,
return 0; return 0;
} }
static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr, static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
struct rec_timing *timing)
{ {
printk(RAM_DEBUG, printk(RAM_DEBUG, " Increasing TAP until low to high transition is found\n");
" Increasing TAP until low to high transition is found\n");
/* /*
* We use a do while loop since it happens that the strobe read * We use a do while loop since it happens that the strobe read
* is inconsistent, with the strobe already high. The current * is inconsistent, with the strobe already high. The current
@ -164,8 +157,7 @@ static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr,
} }
do { do {
if (increase_tap(timing)) { if (increase_tap(timing)) {
printk(BIOS_CRIT, printk(BIOS_CRIT, "Could not find DQS-high on fine search.\n");
"Could not find DQS-high on fine search.\n");
return -1; return -1;
} }
program_timing(timing, channel, lane); program_timing(timing, channel, lane);
@ -176,15 +168,13 @@ static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr,
return 0; return 0;
} }
static int find_dqs_low(u8 channel, u8 lane, u32 addr, static int find_dqs_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing)
struct rec_timing *timing)
{ {
/* Look for DQS low, using quarter steps. */ /* Look for DQS low, using quarter steps. */
printk(RAM_DEBUG, " Increasing medium until DQS LOW is found\n"); printk(RAM_DEBUG, " Increasing medium until DQS LOW is found\n");
while (sampledqs(addr, lane, channel) != DQS_LOW) { while (sampledqs(addr, lane, channel) != DQS_LOW) {
if (increase_medium(timing)) { if (increase_medium(timing)) {
printk(BIOS_CRIT, printk(BIOS_CRIT, "Coarse > 15: DQS tuning failed, halt\n");
"Coarse > 15: DQS tuning failed, halt\n");
return -1; return -1;
} }
program_timing(timing, channel, lane); program_timing(timing, channel, lane);
@ -200,8 +190,7 @@ static int find_dqs_high(u8 channel, u8 lane, u32 addr,
printk(RAM_DEBUG, " Increasing medium until DQS HIGH is found\n"); printk(RAM_DEBUG, " Increasing medium until DQS HIGH is found\n");
while (sampledqs(addr, lane, channel) != DQS_HIGH) { while (sampledqs(addr, lane, channel) != DQS_HIGH) {
if (increase_medium(timing)) { if (increase_medium(timing)) {
printk(BIOS_CRIT, printk(BIOS_CRIT, "Coarse > 16: DQS tuning failed, halt\n");
"Coarse > 16: DQS tuning failed, halt\n");
return -1; return -1;
} }
program_timing(timing, channel, lane); program_timing(timing, channel, lane);
@ -344,8 +333,7 @@ void rcven(struct sysinfo *s)
timing[lane].tap = 0; timing[lane].tap = 0;
timing[lane].pi = 0; timing[lane].pi = 0;
if (calibrate_receive_enable(channel, lane, addr, if (calibrate_receive_enable(channel, lane, addr, &timing[lane]))
&timing[lane]))
die("Receive enable calibration failed\n"); die("Receive enable calibration failed\n");
if (mincoarse > timing[lane].coarse) if (mincoarse > timing[lane].coarse)
mincoarse = timing[lane].coarse; mincoarse = timing[lane].coarse;
@ -359,8 +347,8 @@ void rcven(struct sysinfo *s)
reg8 = 0; reg8 = 0;
else else
reg8 = timing[lane].coarse - mincoarse; reg8 = timing[lane].coarse - mincoarse;
printk(BIOS_DEBUG, "ch %d lane %d: coarse offset: %d;" printk(BIOS_DEBUG,
"medium: %d; tap: %d\n", "ch %d lane %d: coarse offset: %d;medium: %d; tap: %d\n",
channel, lane, reg8, timing[lane].medium, channel, lane, reg8, timing[lane].medium,
timing[lane].tap); timing[lane].tap);
s->rcven_t[channel].coarse_offset[lane] = reg8; s->rcven_t[channel].coarse_offset[lane] = reg8;