Factor out common CAR asm snippets.

This makes the CAR implementations a lot more readable, shorter and
easier to follow, and also reduces the amount of uselessly duplicated code.

For example there are more than 12 open-coded "enable cache" instances
spread all over the place (and 12 "disable cache" ones), multiple
"enable mtrr", "save BIST", "restore BIST", etc. etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-10-01 21:46:04 +00:00
parent 2ba2b553b5
commit dd8367006c
7 changed files with 139 additions and 190 deletions

View File

@@ -21,6 +21,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/car.h>
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
@@ -28,8 +29,7 @@
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
/* Save the BIST result. */
movl %eax, %ebp
save_bist_result()
CacheAsRam:
/* Check whether the processor has HT capability. */
@@ -231,10 +231,7 @@ clear_fixed_var_mtrr_out:
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* Enable cache. */
movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0
enable_cache()
/* Read the range with lodsl. */
movl $CacheBase, %esi
@@ -295,8 +292,7 @@ clear_fixed_var_mtrr_out:
movl $(CacheBase + CacheSize - 4), %eax
movl %eax, %esp
lout:
/* Restore the BIST result. */
movl %ebp, %eax
restore_bist_result()
/* We need to set EBP? No need. */
movl %esp, %ebp
@@ -305,10 +301,7 @@ lout:
/* We don't need CAR from now on. */
/* Disable cache. */
movl %cr0, %eax
orl $(1 << 30), %eax
movl %eax, %cr0
disable_cache()
/* Clear sth. */
movl $MTRRfix4K_C8000_MSR, %ecx
@@ -330,10 +323,7 @@ lout:
movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
wrmsr
/* Enable cache. */
movl %cr0, %eax
andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0
enable_cache();
/* Clear boot_complete flag. */
xorl %ebp, %ebp