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cpu/intel/haswell: Move chip_ops to cpu cluster

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The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.

Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
2021-11-15 20:11:12 +01:00
committed by Felix Held
parent c87814d750
commit dd96ab6987
21 changed files with 58 additions and 138 deletions
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16
src/cpu/intel/haswell/acpi.c
View File

@@ -164,28 +164,22 @@ static void generate_T_state_entries(int core, int cores_per_package)
ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
}
static bool is_s0ix_enabled(void)
static bool is_s0ix_enabled(const struct device *dev)
{
if (!haswell_is_ult())
return false;
const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic || !lapic->chip_info)
return false;
const struct cpu_intel_haswell_config *conf = lapic->chip_info;
const struct cpu_intel_haswell_config *conf = dev->chip_info;
return conf->s0ix_enable;
}
static void generate_C_state_entries(void)
static void generate_C_state_entries(const struct device *dev)
{
acpi_cstate_t acpi_cstate_map[3] = {0};
const int *acpi_cstates;
if (is_s0ix_enabled())
if (is_s0ix_enabled(dev))
acpi_cstates = cstate_set_s0ix;
else if (haswell_is_ult())
acpi_cstates = cstate_set_lp;
@@ -352,7 +346,7 @@ void generate_cpu_entries(const struct device *device)
coreID - 1, cores_per_package);
/* Generate C-state tables */
generate_C_state_entries();
generate_C_state_entries(device);
/* Generate T-state tables */
generate_T_state_entries(

3
src/cpu/intel/haswell/chip.h
View File

@@ -1,8 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Magic value used to locate this chip in the device tree */
#define SPEEDSTEP_APIC_MAGIC 0xACAC
#include <stdbool.h>
#include <stdint.h>

27
src/cpu/intel/haswell/haswell_init.c
View File

@@ -172,18 +172,16 @@ static int pcode_mailbox_write(u32 command, u32 data)
return 0;
}
static struct device *cpu_cluster;
static void initialize_vr_config(void)
{
struct cpu_vr_config vr_config = { 0 };
msr_t msr;
const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (lapic && lapic->chip_info) {
const struct cpu_intel_haswell_config *conf = lapic->chip_info;
vr_config = conf->vr_config;
}
/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
const struct cpu_intel_haswell_config *conf = cpu_cluster->chip_info;
vr_config = conf->vr_config;
printk(BIOS_DEBUG, "Initializing VR config.\n");
@@ -448,18 +446,12 @@ static void configure_c_states(void)
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
static void configure_thermal_target(void)
static void configure_thermal_target(struct device *dev)
{
struct cpu_intel_haswell_config *conf;
struct device *lapic;
/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
struct cpu_intel_haswell_config *conf = dev->bus->dev->chip_info;
msr_t msr;
/* Find pointer to CPU configuration */
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (!lapic || !lapic->chip_info)
return;
conf = lapic->chip_info;
/* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
@@ -551,7 +543,7 @@ static void cpu_core_init(struct device *cpu)
configure_misc();
/* Thermal throttle activation offset */
configure_thermal_target();
configure_thermal_target(cpu);
/* Enable Direct Cache Access */
configure_dca_cap();
@@ -638,6 +630,7 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus)
{
cpu_cluster = cpu_bus->dev;
/* TODO: Handle mp_init_with_smm failure? */
mp_init_with_smm(cpu_bus, &mp_ops);
}